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[201.43.103.101]) by smtp.gmail.com with ESMTPSA id w8-20020a056871060800b0014c8685f229sm514577oan.10.2022.12.21.10.23.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Dec 2022 10:23:13 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza , Bin Meng Subject: [PATCH 00/15] riscv: opensbi boot test and cleanups Date: Wed, 21 Dec 2022 15:22:45 -0300 Message-Id: <20221221182300.307900-1-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.38.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2001:4860:4864:20::2f; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x2f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi, This series starts by adding a simple Avocado smoke test for RISC-V machines that uses opensbi. The newly added test is then used to validate the cleanups made along the way. With this test, running 'make check-avocado' after building all RISC-V targets will run the test as follows: (06/17) tests/avocado/riscv_opensbi.py:RiscvOpensbi.test_riscv64_virt: PASS (0.05 s) (07/17) tests/avocado/riscv_opensbi.py:RiscvOpensbi.test_riscv64_spike: PASS (0.04 s) (08/17) tests/avocado/riscv_opensbi.py:RiscvOpensbi.test_riscv64_sifive_u: PASS (0.06 s) (09/17) tests/avocado/riscv_opensbi.py:RiscvOpensbi.test_riscv32_virt: PASS (0.05 s) (10/17) tests/avocado/riscv_opensbi.py:RiscvOpensbi.test_riscv32_sifive_u: PASS (0.06 s) Note that there are other tests that aren't being run with RISC-V yet. We'll enable them as needed later on. After adding this test, our goal is then to reduce boot code repetition between RISC-V boards and consolidate all boot activities related with the -kernel option in a single function, riscv_load_kernel(). Aside from allowing all boards to load initrd if -initrd is used (see patch 11), no other functional changes were intended. Cc: Alistair Francis Cc: Bin Meng Daniel Henrique Barboza (15): tests/avocado: add RISC-V opensbi boot test hw/riscv/spike: use 'fdt' from MachineState hw/riscv/sifive_u: use 'fdt' from MachineState hw/riscv/boot.c: make riscv_find_firmware() static hw/riscv/boot.c: introduce riscv_default_firmware_name() hw/riscv/spike.c: load initrd right after riscv_load_kernel() hw/riscv: write initrd 'chosen' FDT inside riscv_load_initrd() hw/riscv: write bootargs 'chosen' FDT after riscv_load_kernel() hw/riscv/boot.c: use MachineState in riscv_load_initrd() hw/riscv/boot.c: use MachineState in riscv_load_kernel() hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel() hw/riscv/boot.c: make riscv_load_initrd() static hw/riscv/spike.c: simplify create_fdt() hw/riscv/virt.c: simplify create_fdt() hw/riscv/sifive_u: simplify create_fdt() hw/riscv/boot.c | 137 ++++++++++++++++++++------------- hw/riscv/microchip_pfsoc.c | 19 +---- hw/riscv/opentitan.c | 3 +- hw/riscv/sifive_e.c | 3 +- hw/riscv/sifive_u.c | 51 ++++-------- hw/riscv/spike.c | 53 ++++--------- hw/riscv/virt.c | 38 ++------- include/hw/riscv/boot.h | 6 +- include/hw/riscv/sifive_u.h | 3 - include/hw/riscv/spike.h | 2 - tests/avocado/riscv_opensbi.py | 65 ++++++++++++++++ 11 files changed, 189 insertions(+), 191 deletions(-) create mode 100644 tests/avocado/riscv_opensbi.py -- 2.38.1