From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pj1-f45.google.com (mail-pj1-f45.google.com [209.85.216.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8A0467E for ; Fri, 30 Dec 2022 09:55:00 +0000 (UTC) Received: by mail-pj1-f45.google.com with SMTP id o1-20020a17090a678100b00219cf69e5f0so25351538pjj.2 for ; Fri, 30 Dec 2022 01:55:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=daynix-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=2HDTeomnMfOdczuT9/F20bMQlAjaFMXCpRqH1kdgIVY=; b=P9Ljo6kGW+xXABlWTHQolBfJ92OlshrKeGbeNt/GrqH7QUYhjfdCECOnQT6TSUHFt0 BVmVAq9orDdtalAj8cJy59Toe8NUXr9mGDh5YSq6U1hQ4izys8arYQcQqgrYPJ+4oGUv tfh8nq+ILIaVR6vyApuEdCU+iykOlI1TNZoH4EmL3i6GAEoB/f93QGDdJYs7qpx+xeO+ MCRrEDYCS5hmzgdV4mkghCCVsttFUg698w4d2Tf3VrgLBGjy+lqA+OzLmYca/7Ukj0tU 1SInCBY3SYEfYv27cTfv2QjJSvZOLF+bC/YDogY+/KIVKqRZfkRIz9G1a6largSAZw1Q rHcw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=2HDTeomnMfOdczuT9/F20bMQlAjaFMXCpRqH1kdgIVY=; b=RM5d2/hUfaxx54RHug/cTipZPkUsf8s8CT/2q3toEE/+8SRuE5jKp6Fewmya930ppY vWIW0OlvfgcSpqMqAskS+vlWUhT8IlPVexCL2RY9oZNv/lzPcuP+ZCQ2UqooHK3R9kyn N49ay+bCZ0kRm/pXvn6hGuf+2tHGhOU+HuYn6YKIphTfVKglfNKnTMoiSlRem54ffogd XNxNh1LxVUxTbwsYtYTFXidAKNtmttjNQtJcCnyWzvHeOG3R6kP/1n1/boACWs2sLfm0 AqxTkoREO4+F3IfV06EMY+91k+p66Ax6ac/tdH+P5SGKKDl1LJmCIbOBeNnd+LpBLze2 Xlgg== X-Gm-Message-State: AFqh2krE48L8pDUqUw5A1JCJPI9g4Du/mdSQauZVh8Sz0jZDRm1ngIfi pKy6yoOe2eK/eDC6vU7FE3I29A== X-Google-Smtp-Source: AMrXdXt/fAe2lXnpbEVPcBDmkZY6Wl4VVcSk141fejrUaMn53mFyxFW3jXXtZ/DXOfhybJVp3n0G3w== X-Received: by 2002:a17:903:2312:b0:192:8c7f:2654 with SMTP id d18-20020a170903231200b001928c7f2654mr16330645plh.0.1672394099989; Fri, 30 Dec 2022 01:54:59 -0800 (PST) Received: from fedora.flets-east.jp ([2400:4050:c360:8200:8ae8:3c4:c0da:7419]) by smtp.gmail.com with ESMTPSA id b7-20020a170902650700b00189c536c72asm14487719plk.148.2022.12.30.01.54.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Dec 2022 01:54:59 -0800 (PST) From: Akihiko Odaki To: Cc: Mark Brown , Marc Zyngier , linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, Mathieu Poirier , Oliver Upton , Suzuki K Poulose , Alexandru Elisei , James Morse , Will Deacon , Catalin Marinas , asahi@lists.linux.dev, Alyssa Rosenzweig , Sven Peter , Hector Martin , Akihiko Odaki Subject: [PATCH v5 0/7] KVM: arm64: Normalize cache configuration Date: Fri, 30 Dec 2022 18:54:45 +0900 Message-Id: <20221230095452.181764-1-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.38.1 Precedence: bulk X-Mailing-List: asahi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Before this change, the cache configuration of the physical CPU was exposed to vcpus. This is problematic because the cache configuration a vcpu sees varies when it migrates between vcpus with different cache configurations. Fabricate cache configuration from the sanitized value, which holds the CTR_EL0 value the userspace sees regardless of which physical CPU it resides on. V4 -> V5: - Noted why cache level existence check is unnecessary when fabricating CCSIDR_EL1 value. - Removed FWB check. It is necessary as CLIDR_EL1.{LoUU, LoIUS} on the host are {0, 0} if FWB is enabled, and such a CLIDR_EL1 value sets the IDC bit of the sanitized CTR_EL0 value, which is already checked. - Removed UNDEF injection when reading CCSIDR_EL1 with an invalid CSSELR_EL1 value. - Added a check for CLIDR_EL1.{LoUU,LoC,LoUIS} values set from the userspace. V3 -> V4: - Implemented UNKNOWN system register definition for CCSIDR_EL1 - Added a comment about the relation between CCSIDR_EL1 and FEAT_CCIDX - Squashed "Normalize cache configuration" and "Allow user to set CCSIDR_EL1" The intermediate state between them did not make much sense. - Introduced FIELD_GET to extract CCSIDR_EL1_LineSize. V2 -> V3: - Corrected message for patch "Normalize cache configuration" - Split patch "Normalize cache configuration" - Added handling for CSSELR_EL1.TnD - Added code to ignore RES0 in CSSELR_EL1 - Replaced arm64_ftr_reg_ctrel0.sys_val with read_sanitised_ftr_reg(SYS_CTR_EL0) - Fixed vcpu->arch.ccsidr initialziation - Added CCSIDR_EL1 sanitization - Added FWB check - Added a comment for CACHE_TYPE_SEPARATE - Added MTE tag cache creation code for CLIDR_EL1 fabrication - Removed CLIDR_EL1 reset code for reset caused by guest - Added a comment for CCSIDR2 V2: https://lore.kernel.org/lkml/20221211051700.275761-2-akihiko.odaki@daynix.com/ V1: https://lore.kernel.org/lkml/525ff263-90b3-5b12-da31-171b09f9ad1b@daynix.com/ Akihiko Odaki (6): arm64/sysreg: Convert CCSIDR_EL1 to automatic generation arm64/sysreg: Add CCSIDR2_EL1 arm64/cache: Move CLIDR macro definitions KVM: arm64: Always set HCR_TID2 KVM: arm64: Mask FEAT_CCIDX KVM: arm64: Normalize cache configuration Marc Zyngier (1): arm64: Allow the definition of UNKNOWN system register fields arch/arm64/include/asm/cache.h | 9 + arch/arm64/include/asm/kvm_arm.h | 3 +- arch/arm64/include/asm/kvm_emulate.h | 4 - arch/arm64/include/asm/kvm_host.h | 6 +- arch/arm64/include/asm/sysreg.h | 1 - arch/arm64/kernel/cacheinfo.c | 5 - arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h | 2 - arch/arm64/kvm/reset.c | 1 + arch/arm64/kvm/sys_regs.c | 256 +++++++++++++-------- arch/arm64/tools/gen-sysreg.awk | 20 +- arch/arm64/tools/sysreg | 17 ++ 11 files changed, 212 insertions(+), 112 deletions(-) -- 2.38.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DBECDC4167B for ; Fri, 30 Dec 2022 09:55:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234921AbiL3JzD (ORCPT ); Fri, 30 Dec 2022 04:55:03 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43668 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229505AbiL3JzB (ORCPT ); Fri, 30 Dec 2022 04:55:01 -0500 Received: from mail-pl1-x630.google.com (mail-pl1-x630.google.com [IPv6:2607:f8b0:4864:20::630]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7131C1A807 for ; Fri, 30 Dec 2022 01:55:00 -0800 (PST) Received: by mail-pl1-x630.google.com with SMTP id jn22so21333780plb.13 for ; Fri, 30 Dec 2022 01:55:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=daynix-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=2HDTeomnMfOdczuT9/F20bMQlAjaFMXCpRqH1kdgIVY=; b=P9Ljo6kGW+xXABlWTHQolBfJ92OlshrKeGbeNt/GrqH7QUYhjfdCECOnQT6TSUHFt0 BVmVAq9orDdtalAj8cJy59Toe8NUXr9mGDh5YSq6U1hQ4izys8arYQcQqgrYPJ+4oGUv tfh8nq+ILIaVR6vyApuEdCU+iykOlI1TNZoH4EmL3i6GAEoB/f93QGDdJYs7qpx+xeO+ MCRrEDYCS5hmzgdV4mkghCCVsttFUg698w4d2Tf3VrgLBGjy+lqA+OzLmYca/7Ukj0tU 1SInCBY3SYEfYv27cTfv2QjJSvZOLF+bC/YDogY+/KIVKqRZfkRIz9G1a6largSAZw1Q rHcw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=2HDTeomnMfOdczuT9/F20bMQlAjaFMXCpRqH1kdgIVY=; b=mQj/SLwFhidYO+n1eVOTwUrPJe+HYst7agB7+PQD7Lu8xv/bnfE4SYY3aU2UqlsfX8 dq0nzkvmlbK6jD9T+WhemAN+EufKTWkHQEWJuUead9NZmtpDzEDWnx1UtT6uEld78d/o gM/HMbbbItkjUEC4RYlTo7Ruaik0ICuuk4Ve5ZaD5DO1OCukbF7mcDxMLnJDoPd4Ampd 6ccd4toNzkemxyvt6p8nSvZBG3/SE1UzdIHZRz7XA1UlL/EiMqKmNlvrUuuOjwpDc8I4 QWsudfdda62JxBQ44mi7VqO1aRURyLV9N4kPqmlnq/hG7HpOA3HeVZK7QhWkMPmgKn1k lqQg== X-Gm-Message-State: AFqh2ko6ClCw5ITmnZnudA/2s1nb87aAFOrs1Xtz9E9B9GmpB+5fRblx 0OIOaQ8qaRPGM3YXfssVBH1MUA== X-Google-Smtp-Source: AMrXdXt/fAe2lXnpbEVPcBDmkZY6Wl4VVcSk141fejrUaMn53mFyxFW3jXXtZ/DXOfhybJVp3n0G3w== X-Received: by 2002:a17:903:2312:b0:192:8c7f:2654 with SMTP id d18-20020a170903231200b001928c7f2654mr16330645plh.0.1672394099989; Fri, 30 Dec 2022 01:54:59 -0800 (PST) Received: from fedora.flets-east.jp ([2400:4050:c360:8200:8ae8:3c4:c0da:7419]) by smtp.gmail.com with ESMTPSA id b7-20020a170902650700b00189c536c72asm14487719plk.148.2022.12.30.01.54.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Dec 2022 01:54:59 -0800 (PST) From: Akihiko Odaki Cc: Mark Brown , Marc Zyngier , linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, Mathieu Poirier , Oliver Upton , Suzuki K Poulose , Alexandru Elisei , James Morse , Will Deacon , Catalin Marinas , asahi@lists.linux.dev, Alyssa Rosenzweig , Sven Peter , Hector Martin , Akihiko Odaki Subject: [PATCH v5 0/7] KVM: arm64: Normalize cache configuration Date: Fri, 30 Dec 2022 18:54:45 +0900 Message-Id: <20221230095452.181764-1-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.38.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Before this change, the cache configuration of the physical CPU was exposed to vcpus. This is problematic because the cache configuration a vcpu sees varies when it migrates between vcpus with different cache configurations. Fabricate cache configuration from the sanitized value, which holds the CTR_EL0 value the userspace sees regardless of which physical CPU it resides on. V4 -> V5: - Noted why cache level existence check is unnecessary when fabricating CCSIDR_EL1 value. - Removed FWB check. It is necessary as CLIDR_EL1.{LoUU, LoIUS} on the host are {0, 0} if FWB is enabled, and such a CLIDR_EL1 value sets the IDC bit of the sanitized CTR_EL0 value, which is already checked. - Removed UNDEF injection when reading CCSIDR_EL1 with an invalid CSSELR_EL1 value. - Added a check for CLIDR_EL1.{LoUU,LoC,LoUIS} values set from the userspace. V3 -> V4: - Implemented UNKNOWN system register definition for CCSIDR_EL1 - Added a comment about the relation between CCSIDR_EL1 and FEAT_CCIDX - Squashed "Normalize cache configuration" and "Allow user to set CCSIDR_EL1" The intermediate state between them did not make much sense. - Introduced FIELD_GET to extract CCSIDR_EL1_LineSize. V2 -> V3: - Corrected message for patch "Normalize cache configuration" - Split patch "Normalize cache configuration" - Added handling for CSSELR_EL1.TnD - Added code to ignore RES0 in CSSELR_EL1 - Replaced arm64_ftr_reg_ctrel0.sys_val with read_sanitised_ftr_reg(SYS_CTR_EL0) - Fixed vcpu->arch.ccsidr initialziation - Added CCSIDR_EL1 sanitization - Added FWB check - Added a comment for CACHE_TYPE_SEPARATE - Added MTE tag cache creation code for CLIDR_EL1 fabrication - Removed CLIDR_EL1 reset code for reset caused by guest - Added a comment for CCSIDR2 V2: https://lore.kernel.org/lkml/20221211051700.275761-2-akihiko.odaki@daynix.com/ V1: https://lore.kernel.org/lkml/525ff263-90b3-5b12-da31-171b09f9ad1b@daynix.com/ Akihiko Odaki (6): arm64/sysreg: Convert CCSIDR_EL1 to automatic generation arm64/sysreg: Add CCSIDR2_EL1 arm64/cache: Move CLIDR macro definitions KVM: arm64: Always set HCR_TID2 KVM: arm64: Mask FEAT_CCIDX KVM: arm64: Normalize cache configuration Marc Zyngier (1): arm64: Allow the definition of UNKNOWN system register fields arch/arm64/include/asm/cache.h | 9 + arch/arm64/include/asm/kvm_arm.h | 3 +- arch/arm64/include/asm/kvm_emulate.h | 4 - arch/arm64/include/asm/kvm_host.h | 6 +- arch/arm64/include/asm/sysreg.h | 1 - arch/arm64/kernel/cacheinfo.c | 5 - arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h | 2 - arch/arm64/kvm/reset.c | 1 + arch/arm64/kvm/sys_regs.c | 256 +++++++++++++-------- arch/arm64/tools/gen-sysreg.awk | 20 +- arch/arm64/tools/sysreg | 17 ++ 11 files changed, 212 insertions(+), 112 deletions(-) -- 2.38.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mm01.cs.columbia.edu (mm01.cs.columbia.edu [128.59.11.253]) by smtp.lore.kernel.org (Postfix) with ESMTP id 34ADBC3DA7C for ; Fri, 30 Dec 2022 09:55:05 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id B89994B3E5; Fri, 30 Dec 2022 04:55:04 -0500 (EST) X-Virus-Scanned: at lists.cs.columbia.edu Authentication-Results: mm01.cs.columbia.edu (amavisd-new); dkim=softfail (fail, message has been altered) header.i=@daynix-com.20210112.gappssmtp.com Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id vYD8Q84irH9j; Fri, 30 Dec 2022 04:55:03 -0500 (EST) Received: from mm01.cs.columbia.edu (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 9E7794B4D7; Fri, 30 Dec 2022 04:55:03 -0500 (EST) Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 584064B3E5 for ; Fri, 30 Dec 2022 04:55:02 -0500 (EST) X-Virus-Scanned: at lists.cs.columbia.edu Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id dLcspJVyz8+n for ; Fri, 30 Dec 2022 04:55:01 -0500 (EST) Received: from mail-pj1-f49.google.com (mail-pj1-f49.google.com [209.85.216.49]) by mm01.cs.columbia.edu (Postfix) with ESMTPS id 0BB6A4B286 for ; Fri, 30 Dec 2022 04:55:01 -0500 (EST) Received: by mail-pj1-f49.google.com with SMTP id o8-20020a17090a9f8800b00223de0364beso25336471pjp.4 for ; Fri, 30 Dec 2022 01:55:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=daynix-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=2HDTeomnMfOdczuT9/F20bMQlAjaFMXCpRqH1kdgIVY=; b=P9Ljo6kGW+xXABlWTHQolBfJ92OlshrKeGbeNt/GrqH7QUYhjfdCECOnQT6TSUHFt0 BVmVAq9orDdtalAj8cJy59Toe8NUXr9mGDh5YSq6U1hQ4izys8arYQcQqgrYPJ+4oGUv tfh8nq+ILIaVR6vyApuEdCU+iykOlI1TNZoH4EmL3i6GAEoB/f93QGDdJYs7qpx+xeO+ MCRrEDYCS5hmzgdV4mkghCCVsttFUg698w4d2Tf3VrgLBGjy+lqA+OzLmYca/7Ukj0tU 1SInCBY3SYEfYv27cTfv2QjJSvZOLF+bC/YDogY+/KIVKqRZfkRIz9G1a6largSAZw1Q rHcw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=2HDTeomnMfOdczuT9/F20bMQlAjaFMXCpRqH1kdgIVY=; b=4kZxJU7mYr85YvpaLWuQ4b9nL2iwSZFYswyyVrK4MaIXjxMBZygDc0nop3JhlDY/ek gCczhmb0wOx7JXqrhoffShx2R0ZidxSetAdM9jI5oMEF6s2e/cHvA/MaP5LuhU9D0RfL WRp5I7gUalqwPSbMlvfjTmGu1nE8FdfblJ/ISeQH68Jv1tYH+9KSrKX3EOB3XZzXwv0Q AE86ISHenImlsRK+eWBxOwOZujaPrh9LlN3uhdMnnEIkqu6U5KvlYVAV4FlSp27Aub33 eYMXo4I4vorpzTxFwBsjUpFXPFDvcuIim/sQPhCpFLnsJTb7qIyVQ6xNZ0d5wVMLlQIY y0/w== X-Gm-Message-State: AFqh2kqYchBPEHLnv7SBi2dOkDQiwObJV0nsj/xiQw7cL3g9uMxsHv7Q NsiAy0mNXWZGHdvAJ+QsRNQ+Vg== X-Google-Smtp-Source: AMrXdXt/fAe2lXnpbEVPcBDmkZY6Wl4VVcSk141fejrUaMn53mFyxFW3jXXtZ/DXOfhybJVp3n0G3w== X-Received: by 2002:a17:903:2312:b0:192:8c7f:2654 with SMTP id d18-20020a170903231200b001928c7f2654mr16330645plh.0.1672394099989; Fri, 30 Dec 2022 01:54:59 -0800 (PST) Received: from fedora.flets-east.jp ([2400:4050:c360:8200:8ae8:3c4:c0da:7419]) by smtp.gmail.com with ESMTPSA id b7-20020a170902650700b00189c536c72asm14487719plk.148.2022.12.30.01.54.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Dec 2022 01:54:59 -0800 (PST) From: Akihiko Odaki To: Subject: [PATCH v5 0/7] KVM: arm64: Normalize cache configuration Date: Fri, 30 Dec 2022 18:54:45 +0900 Message-Id: <20221230095452.181764-1-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.38.1 MIME-Version: 1.0 Cc: Alyssa Rosenzweig , Hector Martin , Akihiko Odaki , Mathieu Poirier , Marc Zyngier , Sven Peter , linux-kernel@vger.kernel.org, Will Deacon , Mark Brown , asahi@lists.linux.dev, Catalin Marinas , kvmarm@lists.linux.dev, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org X-BeenThere: kvmarm@lists.cs.columbia.edu X-Mailman-Version: 2.1.14 Precedence: list List-Id: Where KVM/ARM decisions are made List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu Before this change, the cache configuration of the physical CPU was exposed to vcpus. This is problematic because the cache configuration a vcpu sees varies when it migrates between vcpus with different cache configurations. Fabricate cache configuration from the sanitized value, which holds the CTR_EL0 value the userspace sees regardless of which physical CPU it resides on. V4 -> V5: - Noted why cache level existence check is unnecessary when fabricating CCSIDR_EL1 value. - Removed FWB check. It is necessary as CLIDR_EL1.{LoUU, LoIUS} on the host are {0, 0} if FWB is enabled, and such a CLIDR_EL1 value sets the IDC bit of the sanitized CTR_EL0 value, which is already checked. - Removed UNDEF injection when reading CCSIDR_EL1 with an invalid CSSELR_EL1 value. - Added a check for CLIDR_EL1.{LoUU,LoC,LoUIS} values set from the userspace. V3 -> V4: - Implemented UNKNOWN system register definition for CCSIDR_EL1 - Added a comment about the relation between CCSIDR_EL1 and FEAT_CCIDX - Squashed "Normalize cache configuration" and "Allow user to set CCSIDR_EL1" The intermediate state between them did not make much sense. - Introduced FIELD_GET to extract CCSIDR_EL1_LineSize. V2 -> V3: - Corrected message for patch "Normalize cache configuration" - Split patch "Normalize cache configuration" - Added handling for CSSELR_EL1.TnD - Added code to ignore RES0 in CSSELR_EL1 - Replaced arm64_ftr_reg_ctrel0.sys_val with read_sanitised_ftr_reg(SYS_CTR_EL0) - Fixed vcpu->arch.ccsidr initialziation - Added CCSIDR_EL1 sanitization - Added FWB check - Added a comment for CACHE_TYPE_SEPARATE - Added MTE tag cache creation code for CLIDR_EL1 fabrication - Removed CLIDR_EL1 reset code for reset caused by guest - Added a comment for CCSIDR2 V2: https://lore.kernel.org/lkml/20221211051700.275761-2-akihiko.odaki@daynix.com/ V1: https://lore.kernel.org/lkml/525ff263-90b3-5b12-da31-171b09f9ad1b@daynix.com/ Akihiko Odaki (6): arm64/sysreg: Convert CCSIDR_EL1 to automatic generation arm64/sysreg: Add CCSIDR2_EL1 arm64/cache: Move CLIDR macro definitions KVM: arm64: Always set HCR_TID2 KVM: arm64: Mask FEAT_CCIDX KVM: arm64: Normalize cache configuration Marc Zyngier (1): arm64: Allow the definition of UNKNOWN system register fields arch/arm64/include/asm/cache.h | 9 + arch/arm64/include/asm/kvm_arm.h | 3 +- arch/arm64/include/asm/kvm_emulate.h | 4 - arch/arm64/include/asm/kvm_host.h | 6 +- arch/arm64/include/asm/sysreg.h | 1 - arch/arm64/kernel/cacheinfo.c | 5 - arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h | 2 - arch/arm64/kvm/reset.c | 1 + arch/arm64/kvm/sys_regs.c | 256 +++++++++++++-------- arch/arm64/tools/gen-sysreg.awk | 20 +- arch/arm64/tools/sysreg | 17 ++ 11 files changed, 212 insertions(+), 112 deletions(-) -- 2.38.1 _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2B4FCC4167B for ; Fri, 30 Dec 2022 13:33:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=jRUGkx/LmnV9Ws9vcaLcVn9SeYLrJMcCM3QXG7M2e3I=; b=DBFSQYdxAusvPv FC95ZEsBD50P0XR3/bm4uYC5XawGRjBHIc3hsniXNOfo/jLcF/TYCpo88/N4aSWPh89sh7uvuDxYr Nl2UhqOBaD+BCN8GaNGBSR1NRgbiXT5jXVJpbYRi63n9ZCQmYLU3uZshJf/AJjj2LDcrmMTTtkc/O XijEpci12PKZzip6xwt28ea5WiqBYnhiiEmeSQtNXUdUyXcz08llRY/Sj7nFalUh/HMMPmypQaThx Hcsa+yeRHHbEQptJvD6EXs1La4/lOIVAUzNWY1GJc4tFNjE8Ag8fWZd70QDV7LeUfovQGNlOMJBtP RMoadsGfuKfhkCVQOJpg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pBFUC-009Yhf-Ia; Fri, 30 Dec 2022 13:31:48 +0000 Received: from mail-pj1-x1030.google.com ([2607:f8b0:4864:20::1030]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1pBC6T-007uIZ-M7 for linux-arm-kernel@lists.infradead.org; Fri, 30 Dec 2022 09:55:08 +0000 Received: by mail-pj1-x1030.google.com with SMTP id m7-20020a17090a730700b00225ebb9cd01so13439649pjk.3 for ; Fri, 30 Dec 2022 01:55:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=daynix-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=2HDTeomnMfOdczuT9/F20bMQlAjaFMXCpRqH1kdgIVY=; b=P9Ljo6kGW+xXABlWTHQolBfJ92OlshrKeGbeNt/GrqH7QUYhjfdCECOnQT6TSUHFt0 BVmVAq9orDdtalAj8cJy59Toe8NUXr9mGDh5YSq6U1hQ4izys8arYQcQqgrYPJ+4oGUv tfh8nq+ILIaVR6vyApuEdCU+iykOlI1TNZoH4EmL3i6GAEoB/f93QGDdJYs7qpx+xeO+ MCRrEDYCS5hmzgdV4mkghCCVsttFUg698w4d2Tf3VrgLBGjy+lqA+OzLmYca/7Ukj0tU 1SInCBY3SYEfYv27cTfv2QjJSvZOLF+bC/YDogY+/KIVKqRZfkRIz9G1a6largSAZw1Q rHcw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=2HDTeomnMfOdczuT9/F20bMQlAjaFMXCpRqH1kdgIVY=; b=haf93aIENSytZHlFYX32AeN4pEQEsqJ0hKFmKOo+hD2bgDE4YF9sJjhEDuLecH8C1q kM35p6VhRIR8VKlgs+wk7RJ1/jkpprHu4I8ylriCP6u4hMldFFWJm40GUTvFEN+LJ7P6 /q9M3uH6HtShrJCvM8uAot8QfEZChNHdHo/K7phPov7GZQfXBfAmyRv0GHn66CVzIQNV w+Qw080aQMkPzGYAtMNZkiY6C3IHPPyUyhlZWUiRmqna5PpmHVRA6o6n3sDgvfY+FYSH w37OdrJPKL2uI37ktSLJvQRNk4LU8aonGZABzRk91YfbftRdRAcYkfkxge0U8WNcw8jt kWDg== X-Gm-Message-State: AFqh2krV1bpyyKzMq7hLHRvgngPFbVhvkNui7lMmqdZecmF2H9CylpM6 hQ3NzQWYme7Himob7n7v7h2gRTVhbiBt4AeY7pE= X-Google-Smtp-Source: AMrXdXt/fAe2lXnpbEVPcBDmkZY6Wl4VVcSk141fejrUaMn53mFyxFW3jXXtZ/DXOfhybJVp3n0G3w== X-Received: by 2002:a17:903:2312:b0:192:8c7f:2654 with SMTP id d18-20020a170903231200b001928c7f2654mr16330645plh.0.1672394099989; Fri, 30 Dec 2022 01:54:59 -0800 (PST) Received: from fedora.flets-east.jp ([2400:4050:c360:8200:8ae8:3c4:c0da:7419]) by smtp.gmail.com with ESMTPSA id b7-20020a170902650700b00189c536c72asm14487719plk.148.2022.12.30.01.54.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Dec 2022 01:54:59 -0800 (PST) From: Akihiko Odaki To: Cc: Mark Brown , Marc Zyngier , linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, Mathieu Poirier , Oliver Upton , Suzuki K Poulose , Alexandru Elisei , James Morse , Will Deacon , Catalin Marinas , asahi@lists.linux.dev, Alyssa Rosenzweig , Sven Peter , Hector Martin , Akihiko Odaki Subject: [PATCH v5 0/7] KVM: arm64: Normalize cache configuration Date: Fri, 30 Dec 2022 18:54:45 +0900 Message-Id: <20221230095452.181764-1-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.38.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221230_015505_788955_A84CC330 X-CRM114-Status: GOOD ( 11.91 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Before this change, the cache configuration of the physical CPU was exposed to vcpus. This is problematic because the cache configuration a vcpu sees varies when it migrates between vcpus with different cache configurations. Fabricate cache configuration from the sanitized value, which holds the CTR_EL0 value the userspace sees regardless of which physical CPU it resides on. V4 -> V5: - Noted why cache level existence check is unnecessary when fabricating CCSIDR_EL1 value. - Removed FWB check. It is necessary as CLIDR_EL1.{LoUU, LoIUS} on the host are {0, 0} if FWB is enabled, and such a CLIDR_EL1 value sets the IDC bit of the sanitized CTR_EL0 value, which is already checked. - Removed UNDEF injection when reading CCSIDR_EL1 with an invalid CSSELR_EL1 value. - Added a check for CLIDR_EL1.{LoUU,LoC,LoUIS} values set from the userspace. V3 -> V4: - Implemented UNKNOWN system register definition for CCSIDR_EL1 - Added a comment about the relation between CCSIDR_EL1 and FEAT_CCIDX - Squashed "Normalize cache configuration" and "Allow user to set CCSIDR_EL1" The intermediate state between them did not make much sense. - Introduced FIELD_GET to extract CCSIDR_EL1_LineSize. V2 -> V3: - Corrected message for patch "Normalize cache configuration" - Split patch "Normalize cache configuration" - Added handling for CSSELR_EL1.TnD - Added code to ignore RES0 in CSSELR_EL1 - Replaced arm64_ftr_reg_ctrel0.sys_val with read_sanitised_ftr_reg(SYS_CTR_EL0) - Fixed vcpu->arch.ccsidr initialziation - Added CCSIDR_EL1 sanitization - Added FWB check - Added a comment for CACHE_TYPE_SEPARATE - Added MTE tag cache creation code for CLIDR_EL1 fabrication - Removed CLIDR_EL1 reset code for reset caused by guest - Added a comment for CCSIDR2 V2: https://lore.kernel.org/lkml/20221211051700.275761-2-akihiko.odaki@daynix.com/ V1: https://lore.kernel.org/lkml/525ff263-90b3-5b12-da31-171b09f9ad1b@daynix.com/ Akihiko Odaki (6): arm64/sysreg: Convert CCSIDR_EL1 to automatic generation arm64/sysreg: Add CCSIDR2_EL1 arm64/cache: Move CLIDR macro definitions KVM: arm64: Always set HCR_TID2 KVM: arm64: Mask FEAT_CCIDX KVM: arm64: Normalize cache configuration Marc Zyngier (1): arm64: Allow the definition of UNKNOWN system register fields arch/arm64/include/asm/cache.h | 9 + arch/arm64/include/asm/kvm_arm.h | 3 +- arch/arm64/include/asm/kvm_emulate.h | 4 - arch/arm64/include/asm/kvm_host.h | 6 +- arch/arm64/include/asm/sysreg.h | 1 - arch/arm64/kernel/cacheinfo.c | 5 - arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h | 2 - arch/arm64/kvm/reset.c | 1 + arch/arm64/kvm/sys_regs.c | 256 +++++++++++++-------- arch/arm64/tools/gen-sysreg.awk | 20 +- arch/arm64/tools/sysreg | 17 ++ 11 files changed, 212 insertions(+), 112 deletions(-) -- 2.38.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel