From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from out2-smtp.messagingengine.com (out2-smtp.messagingengine.com [66.111.4.26]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0EF852F44 for ; Sat, 31 Dec 2022 16:04:05 +0000 (UTC) Received: from compute5.internal (compute5.nyi.internal [10.202.2.45]) by mailout.nyi.internal (Postfix) with ESMTP id E17505C00CA; Sat, 31 Dec 2022 11:04:04 -0500 (EST) Received: from mailfrontend2 ([10.202.2.163]) by compute5.internal (MEProxy); Sat, 31 Dec 2022 11:04:04 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sholland.org; h= cc:cc:content-transfer-encoding:date:date:from:from:in-reply-to :message-id:mime-version:reply-to:sender:subject:subject:to:to; s=fm3; t=1672502644; x=1672589044; bh=xWE0lT6NaS/AHVoUWn03I8qZ2 RF4KER8K841iF6ca5E=; b=ERRgjIq669xz32IXLnN4VpdajHn1WgfVzs/8rY3NO bjeZ/v3UgLJYT/qISuvf8LbiCetSVa9p3FeVfQ2pWvXZ/cJw63MLSTGoC4WrIRZ3 hUlHZvG61TgTFaO7MfOnmTj9/a4G+EAmEcS+ZYHK5uMrZuFmWlp0P9Q8Gs8HdrMM kFCn3iQckWrV8BNjmx+KNDUN2Qo5AXHcMEWpkETFFfJgQK8rk+dEGOZLOJZ4gmxi UWhr/TzdqFDlu76w7ZqWMUISlR8AsMCp9pCjacF6A/j+MoNFz4R+AgEk481QfbOm DN7Y8QdOQ5Xin5ql4hiOZtfkrh+rHK8lY2Lr+lkz+4dEQ== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding:date:date :feedback-id:feedback-id:from:from:in-reply-to:message-id :mime-version:reply-to:sender:subject:subject:to:to:x-me-proxy :x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s=fm2; t= 1672502644; x=1672589044; bh=xWE0lT6NaS/AHVoUWn03I8qZ2RF4KER8K84 1iF6ca5E=; b=YoEROOA9LgPRbDQQqDVGZ8OGREl/8S4SZ0324CF/Z4piDyCosbs 9/OHg+kyevz6h0cMSJQ0JOfsiU2s9QVU6339P0XU9PNY7Z1BUi3dmE+jc9iECMz5 njOzNrwXqIz4iBNfDblH77GGBgp9hjEQ6UUb0X0H3cqgqxHUijyoQH0OwK1K4gkM MpU30CchqyVVlIYghdlMmx51luUnWdXTb2pO+F71owsGG56aP4QLaMSS0hXrAAPm Fx9cG2EcPKY2//lnR90tB4DQuiV39l4BPVRURJrzSxXaVxoBzKdKn54V9bgIbENw x0mD+9TUsO7pb8JNO7wsTSrmjQj+BUTcHLQ== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvhedrieekgdekfecutefuodetggdotefrodftvf curfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfghnecu uegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmdenuc fjughrpefhvfevufffkffoggfgsedtkeertdertddtnecuhfhrohhmpefurghmuhgvlhcu jfholhhlrghnugcuoehsrghmuhgvlhesshhhohhllhgrnhgurdhorhhgqeenucggtffrrg htthgvrhhnpedvtdelueegfeejtedujedvudejteetheevleekvdfgteegtddvieekudfh leegveenucffohhmrghinhepghhithhhuhgsrdgtohhmnecuvehluhhsthgvrhfuihiivg eptdenucfrrghrrghmpehmrghilhhfrhhomhepshgrmhhuvghlsehshhholhhlrghnugdr ohhrgh X-ME-Proxy: Feedback-ID: i0ad843c9:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Sat, 31 Dec 2022 11:04:03 -0500 (EST) From: Samuel Holland To: Chen-Yu Tsai , Jernej Skrabec , Krzysztof Kozlowski , Rob Herring Cc: Samuel Holland , Philipp Zabel , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev Subject: [PATCH 0/2] Allwinner power domain support Date: Sat, 31 Dec 2022 10:04:00 -0600 Message-Id: <20221231160402.16157-1-samuel@sholland.org> X-Mailer: git-send-email 2.37.4 Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit This series adds support for the power controller found in D1 and other recent Allwinner SoCs. There is no first-party documentation, but there are a couple of vendor drivers for different hardware revisions[1][2], and the register definitions were easy to verify empirically. I have tested this driver on D1 with the video engine. There is no DT update patch here to avoid dependencies between series. The example in the binding is what will go in the D1 DT. [1]: https://github.com/mangopi-sbc/tina-linux-5.4/blob/main/drivers/soc/sunxi/gpu_domain.c [1]: https://github.com/mangopi-sbc/tina-linux-5.4/blob/main/drivers/soc/sunxi/pm_domains.c Samuel Holland (2): dt-bindings: power: Add Allwinner D1 PPU soc: sunxi: Add Allwinner D1 PPU driver .../power/allwinner,sun20i-d1-ppu.yaml | 54 +++++ drivers/soc/sunxi/Kconfig | 9 + drivers/soc/sunxi/Makefile | 1 + drivers/soc/sunxi/sun20i-ppu.c | 207 ++++++++++++++++++ .../power/allwinner,sun20i-d1-ppu.h | 10 + 5 files changed, 281 insertions(+) create mode 100644 Documentation/devicetree/bindings/power/allwinner,sun20i-d1-ppu.yaml create mode 100644 drivers/soc/sunxi/sun20i-ppu.c create mode 100644 include/dt-bindings/power/allwinner,sun20i-d1-ppu.h -- 2.37.4 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BE64AC4332F for ; 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Sat, 31 Dec 2022 11:04:03 -0500 (EST) From: Samuel Holland To: Chen-Yu Tsai , Jernej Skrabec , Krzysztof Kozlowski , Rob Herring Cc: Samuel Holland , Philipp Zabel , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev Subject: [PATCH 0/2] Allwinner power domain support Date: Sat, 31 Dec 2022 10:04:00 -0600 Message-Id: <20221231160402.16157-1-samuel@sholland.org> X-Mailer: git-send-email 2.37.4 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221231_080412_399395_B683ACC9 X-CRM114-Status: GOOD ( 10.72 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This series adds support for the power controller found in D1 and other recent Allwinner SoCs. There is no first-party documentation, but there are a couple of vendor drivers for different hardware revisions[1][2], and the register definitions were easy to verify empirically. I have tested this driver on D1 with the video engine. There is no DT update patch here to avoid dependencies between series. The example in the binding is what will go in the D1 DT. [1]: https://github.com/mangopi-sbc/tina-linux-5.4/blob/main/drivers/soc/sunxi/gpu_domain.c [1]: https://github.com/mangopi-sbc/tina-linux-5.4/blob/main/drivers/soc/sunxi/pm_domains.c Samuel Holland (2): dt-bindings: power: Add Allwinner D1 PPU soc: sunxi: Add Allwinner D1 PPU driver .../power/allwinner,sun20i-d1-ppu.yaml | 54 +++++ drivers/soc/sunxi/Kconfig | 9 + drivers/soc/sunxi/Makefile | 1 + drivers/soc/sunxi/sun20i-ppu.c | 207 ++++++++++++++++++ .../power/allwinner,sun20i-d1-ppu.h | 10 + 5 files changed, 281 insertions(+) create mode 100644 Documentation/devicetree/bindings/power/allwinner,sun20i-d1-ppu.yaml create mode 100644 drivers/soc/sunxi/sun20i-ppu.c create mode 100644 include/dt-bindings/power/allwinner,sun20i-d1-ppu.h -- 2.37.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel