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[71.56.217.229]) by smtp.gmail.com with ESMTPSA id o13-20020a0566022e0d00b006bb5af55ddfsm1659164iow.19.2023.01.07.13.57.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Jan 2023 13:57:51 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Cc: Simon Glass , Jeffy Chen , Kever Yang , Philipp Tomsich , huang lin Subject: [PATCH v2 13/14] rockchip: Enable bootstage on rockpro64 Date: Sat, 7 Jan 2023 14:57:30 -0700 Message-Id: <20230107215731.484317-14-sjg@chromium.org> X-Mailer: git-send-email 2.39.0.314.g84b9a713c41-goog In-Reply-To: <20230107215731.484317-4-sjg@chromium.org> References: <20230107215731.484317-4-sjg@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean This board is useful for benchmarking overall U-Boot performance. Enable the bootstage feature so we get a report. Since this returns to the boot rom before finishing executing board_init_r() in SPL, add a few bootstage calls so that we can collect timing from TPL. For the stash region, use a portion of SRAM, 64KB below the stack top. This allows the TPL image to be up to nearly 120KB (it is typically about 64KB). SPL normally runs from SDRAM at 0, so can use the same stash region. Signed-off-by: Simon Glass --- Changes in v2: - Drop unwanted debugging arch/arm/mach-rockchip/tpl.c | 16 +++++++++++++--- configs/rockpro64-rk3399_defconfig | 8 ++++++++ 2 files changed, 21 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-rockchip/tpl.c b/arch/arm/mach-rockchip/tpl.c index ed46a9ad286..fdd0c592b3e 100644 --- a/arch/arm/mach-rockchip/tpl.c +++ b/arch/arm/mach-rockchip/tpl.c @@ -4,6 +4,7 @@ */ #include +#include #include #include #include @@ -70,15 +71,15 @@ void board_init_f(ulong dummy) U_BOOT_TIME ")\n"); #endif #endif + /* Init secure timer */ + rockchip_stimer_init(); + ret = spl_early_init(); if (ret) { debug("spl_early_init() failed: %d\n", ret); hang(); } - /* Init secure timer */ - rockchip_stimer_init(); - /* Init ARM arch timer */ if (IS_ENABLED(CONFIG_SYS_ARCH_TIMER)) timer_init(); @@ -93,6 +94,15 @@ void board_init_f(ulong dummy) int board_return_to_bootrom(struct spl_image_info *spl_image, struct spl_boot_device *bootdev) { +#ifdef CONFIG_BOOTSTAGE_STASH + int ret; + + bootstage_mark_name(BOOTSTAGE_ID_END_TPL, "end tpl"); + ret = bootstage_stash((void *)CONFIG_BOOTSTAGE_STASH_ADDR, + CONFIG_BOOTSTAGE_STASH_SIZE); + if (ret) + debug("Failed to stash bootstage: err=%d\n", ret); +#endif back_to_bootrom(BROM_BOOT_NEXTSTAGE); return 0; diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig index 5b8d678f6bb..2f1ae156bd4 100644 --- a/configs/rockpro64-rk3399_defconfig +++ b/configs/rockpro64-rk3399_defconfig @@ -9,6 +9,7 @@ CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-rockpro64" CONFIG_ROCKCHIP_RK3399=y CONFIG_TARGET_ROCKPRO64_RK3399=y +CONFIG_BOOTSTAGE_STASH_ADDR=0xff8e0000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -17,6 +18,12 @@ CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 +CONFIG_BOOTSTAGE=y +CONFIG_SPL_BOOTSTAGE=y +CONFIG_TPL_BOOTSTAGE=y +CONFIG_BOOTSTAGE_REPORT=y +CONFIG_SPL_BOOTSTAGE_RECORD_COUNT=10 +CONFIG_BOOTSTAGE_STASH=y CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rockpro64.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y @@ -40,6 +47,7 @@ CONFIG_CMD_PCI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y +CONFIG_CMD_BOOTSTAGE=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_SPI_FLASH=y -- 2.39.0.314.g84b9a713c41-goog