From: "Jouni Högander" <jouni.hogander@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 1/2] drm/i915/psr: Implement Wa_14014971492
Date: Wed, 18 Jan 2023 10:51:59 +0200 [thread overview]
Message-ID: <20230118085200.1017626-2-jouni.hogander@intel.com> (raw)
In-Reply-To: <20230118085200.1017626-1-jouni.hogander@intel.com>
Implement Wa_14014971492 and apply it for affected platforms.
Bspec: 52890, 54369, 55378, 66624
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
drivers/gpu/drm/i915/display/intel_psr.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 7d4a15a283a0..24900a790508 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1842,6 +1842,11 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
if (full_update)
goto skip_sel_fetch_set_loop;
+ /* Wa_14014971492 */
+ if ((IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
+ IS_DISPLAY_VER(dev_priv, 12, 13)) && crtc_state->splitter.enable)
+ pipe_clip.y1 = 0;
+
ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
if (ret)
return ret;
--
2.34.1
next prev parent reply other threads:[~2023-01-18 8:52 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-18 8:51 [Intel-gfx] [PATCH 0/2] drm/i915/psr: PSR related workarounds Jouni Högander
2023-01-18 8:51 ` Jouni Högander [this message]
2023-01-23 21:00 ` [Intel-gfx] [PATCH 1/2] drm/i915/psr: Implement Wa_14014971492 Rodrigo Vivi
2023-01-24 10:28 ` Hogander, Jouni
2023-01-18 8:52 ` [Intel-gfx] [PATCH 2/2] drm/i915/mtl: Apply Wa_14013475917 for all MTL steppings Jouni Högander
2023-01-18 9:37 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/psr: PSR related workarounds Patchwork
2023-01-19 8:37 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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