[PATCH v2 0/2] arm64: dts: qcom: sm8550: Add PCIe HC and PHY support

[PATCH v2 0/2] arm64: dts: qcom: sm8550: Add PCIe HC and PHY support

[Abel Vesa]

This patchset adds PCIe controllers and PHYs support to SM8550 platform
and enables them on the MTP board.

The v1 was here:
https://lore.kernel.org/all/20221116130430.2812173-1-abel.vesa@linaro.org/

Changes since v1:
 * ordered pcie related nodes alphabetically in MTP dts
 * dropped the pipe_mux, phy_pipe and ref clocks from the pcie nodes
 * dropped the child node from the phy nodes, like Johan suggested,
   and updated to use the sc8280xp binding scheme
 * changed "pcie_1_nocsr_com_phy_reset" 2nd reset name of pcie1_phy
   to "nocsr"
 * reordered all pcie nodes properties to look similar to the ones
   from sc8280xp

Abel Vesa (2):
  arm64: dts: qcom: sm8550: Add PCIe PHYs and controllers nodes
  arm64: dts: qcom: sm8550-mtp: Add PCIe PHYs and controllers nodes

 arch/arm64/boot/dts/qcom/sm8550-mtp.dts |  29 ++++
 arch/arm64/boot/dts/qcom/sm8550.dtsi    | 213 +++++++++++++++++++++++-
 2 files changed, 239 insertions(+), 3 deletions(-)

-- 
2.34.1

[PATCH v2 1/2] arm64: dts: qcom: sm8550: Add PCIe PHYs and controllers nodes

[Abel Vesa]

Add PCIe controllers and PHY nodes.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
---
 arch/arm64/boot/dts/qcom/sm8550.dtsi | 213 ++++++++++++++++++++++++++-
 1 file changed, 210 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index 3d47281a276b..a78068cbf95f 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -646,9 +646,9 @@ gcc: clock-controller@100000 {
 			#reset-cells = <1>;
 			#power-domain-cells = <1>;
 			clocks = <&bi_tcxo_div2>, <&sleep_clk>,
-				 <0>,
-				 <0>,
-				 <0>,
+				 <&pcie0_phy>,
+				 <&pcie1_phy>,
+				 <&pcie_1_phy_aux_clk>,
 				 <&ufs_mem_phy 0>,
 				 <&ufs_mem_phy 1>,
 				 <&ufs_mem_phy 2>,
@@ -1547,6 +1547,213 @@ mmss_noc: interconnect@1780000 {
 			qcom,bcm-voters = <&apps_bcm_voter>;
 		};
 
+		pcie0: pci@1c00000 {
+			device_type = "pci";
+			compatible = "qcom,pcie-sm8550";
+			reg = <0 0x01c00000 0 0x3000>,
+			      <0 0x60000000 0 0xf1d>,
+			      <0 0x60000f20 0 0xa8>,
+			      <0 0x60001000 0 0x1000>,
+			      <0 0x60100000 0 0x100000>;
+			reg-names = "parf", "dbi", "elbi", "atu", "config";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
+				 <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>;
+			bus-range = <0x00 0xff>;
+
+			dma-coherent;
+
+			linux,pci-domain = <0>;
+			num-lanes = <2>;
+
+			interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "msi";
+
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 0x7>;
+			interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+					<0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+					<0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+					<0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+			clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
+				 <&gcc GCC_PCIE_0_AUX_CLK>,
+				 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+				 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
+				 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
+				 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
+				 <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>,
+				 <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>;
+			clock-names = "pipe",
+				      "aux",
+				      "cfg",
+				      "bus_master",
+				      "bus_slave",
+				      "slave_q2a",
+				      "ddrss_sf_tbu",
+				      "aggre0";
+
+			interconnect-names = "pcie-mem";
+			interconnects = <&pcie_noc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>;
+
+			iommus = <&apps_smmu 0x1400 0x7f>;
+			iommu-map = <0x0   &apps_smmu 0x1400 0x1>,
+				    <0x100 &apps_smmu 0x1401 0x1>;
+
+			resets = <&gcc GCC_PCIE_0_BCR>;
+			reset-names = "pci";
+
+			power-domains = <&gcc PCIE_0_GDSC>;
+
+			phys = <&pcie0_phy>;
+			phy-names = "pciephy";
+
+			perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
+			wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
+
+			pinctrl-names = "default";
+			pinctrl-0 = <&pcie0_default_state>;
+
+			status = "disabled";
+		};
+
+		pcie0_phy: phy@1c06000 {
+			compatible = "qcom,sm8550-qmp-gen3x2-pcie-phy";
+			reg = <0 0x01c06000 0 0x2000>;
+
+			clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
+				 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+				 <&tcsr TCSR_PCIE_0_CLKREF_EN>,
+				 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
+				 <&gcc GCC_PCIE_0_PIPE_CLK>;
+			clock-names = "aux", "cfg_ahb", "ref", "rchng",
+				      "pipe";
+
+			resets = <&gcc GCC_PCIE_0_PHY_BCR>;
+			reset-names = "phy";
+
+			assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
+			assigned-clock-rates = <100000000>;
+
+			power-domains = <&gcc PCIE_0_PHY_GDSC>;
+
+			#clock-cells = <0>;
+			clock-output-names = "pcie0_pipe_clk";
+
+			#phy-cells = <0>;
+
+			status = "disabled";
+		};
+
+		pcie1: pci@1c08000 {
+			device_type = "pci";
+			compatible = "qcom,pcie-sm8550";
+			reg = <0x0 0x01c08000 0x0 0x3000>,
+			      <0x0 0x40000000 0x0 0xf1d>,
+			      <0x0 0x40000f20 0x0 0xa8>,
+			      <0x0 0x40001000 0x0 0x1000>,
+			      <0x0 0x40100000 0x0 0x100000>;
+			reg-names = "parf", "dbi", "elbi", "atu", "config";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			ranges = <0x01000000 0x0 0x40200000 0 0x40200000 0x0 0x100000>,
+				 <0x02000000 0x0 0x40300000 0 0x40300000 0x0 0x1fd00000>;
+			bus-range = <0x00 0xff>;
+
+			dma-coherent;
+
+			linux,pci-domain = <1>;
+			num-lanes = <2>;
+
+			interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "msi";
+
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 0x7>;
+			interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+					<0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+					<0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+					<0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+			clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
+				 <&gcc GCC_PCIE_1_AUX_CLK>,
+				 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
+				 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
+				 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
+				 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
+				 <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>,
+				 <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
+				 <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>;
+			clock-names = "pipe",
+				      "aux",
+				      "cfg",
+				      "bus_master",
+				      "bus_slave",
+				      "slave_q2a",
+				      "ddrss_sf_tbu",
+				      "aggre1",
+				      "cnoc_pcie_sf_axi";
+
+			assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
+			assigned-clock-rates = <19200000>;
+
+			interconnect-names = "pcie-mem";
+			interconnects = <&pcie_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>;
+
+			iommus = <&apps_smmu 0x1480 0x7f>;
+			iommu-map = <0x0   &apps_smmu 0x1480 0x1>,
+				    <0x100 &apps_smmu 0x1481 0x1>;
+
+			resets = <&gcc GCC_PCIE_1_BCR>,
+				<&gcc GCC_PCIE_1_LINK_DOWN_BCR>;
+			reset-names = "pci",
+				"pcie_1_link_down_reset";
+
+			power-domains = <&gcc PCIE_1_GDSC>;
+
+			phys = <&pcie1_phy>;
+			phy-names = "pciephy";
+
+			perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
+			enable-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>;
+
+			pinctrl-names = "default";
+			pinctrl-0 = <&pcie1_default_state>;
+
+			status = "disabled";
+		};
+
+		pcie1_phy: phy@1c0e000 {
+			compatible = "qcom,sm8550-qmp-gen4x2-pcie-phy";
+			reg = <0x0 0x01c0e000 0x0 0x2000>;
+
+			clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
+				 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
+				 <&tcsr TCSR_PCIE_1_CLKREF_EN>,
+				 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>,
+				 <&gcc GCC_PCIE_1_PIPE_CLK>,
+				 <&gcc GCC_PCIE_1_PHY_AUX_CLK>;
+			clock-names = "aux", "cfg_ahb", "ref", "rchng",
+				      "pipe", "aux_phy";
+
+			resets = <&gcc GCC_PCIE_1_PHY_BCR>,
+				 <&gcc GCC_PCIE_1_NOCSR_COM_PHY_BCR>;
+			reset-names = "phy", "nocsr";
+
+			assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
+			assigned-clock-rates = <100000000>;
+
+			power-domains = <&gcc PCIE_1_PHY_GDSC>;
+
+			#clock-cells = <0>;
+			clock-output-names = "pcie1_pipe_clk";
+
+			#phy-cells = <0>;
+
+			status = "disabled";
+		};
+
 		cryptobam: dma-controller@1dc4000 {
 			compatible = "qcom,bam-v1.7.0";
 			reg = <0x0 0x01dc4000 0x0 0x28000>;
-- 
2.34.1

[PATCH v2 2/2] arm64: dts: qcom: sm8550-mtp: Add PCIe PHYs and controllers nodes

[Abel Vesa]

Enable PCIe controllers and PHYs nodes on SM8550 MTP board.

Co-developed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
---
 arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 29 +++++++++++++++++++++++++
 1 file changed, 29 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts
index 81fcbdc6bdc4..b69ded9c4b57 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts
@@ -359,6 +359,35 @@ vreg_l3g_1p2: ldo3 {
 	};
 };
 
+&pcie_1_phy_aux_clk {
+	clock-frequency = <1000>;
+};
+
+&pcie0 {
+	wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
+	perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
+
+&pcie0_phy {
+	vdda-phy-supply = <&vreg_l1e_0p88>;
+	vdda-pll-supply = <&vreg_l3e_1p2>;
+	status = "okay";
+};
+
+&pcie1 {
+	wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>;
+	perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
+
+&pcie1_phy {
+	vdda-phy-supply = <&vreg_l3c_0p91>;
+	vdda-pll-supply = <&vreg_l3e_1p2>;
+	vdda-qref-supply = <&vreg_l1e_0p88>;
+	status = "okay";
+};
+
 &pm8550_gpios {
 	sdc2_card_det_n: sdc2-card-det-state {
 		pins = "gpio12";
-- 
2.34.1

Re: [PATCH v2 0/2] arm64: dts: qcom: sm8550: Add PCIe HC and PHY support

[Bjorn Andersson]

On Thu, 19 Jan 2023 01:05:24 +0200, Abel Vesa wrote:
> This patchset adds PCIe controllers and PHYs support to SM8550 platform
> and enables them on the MTP board.
> 
> The v1 was here:
> https://lore.kernel.org/all/20221116130430.2812173-1-abel.vesa@linaro.org/
> 
> Changes since v1:
>  * ordered pcie related nodes alphabetically in MTP dts
>  * dropped the pipe_mux, phy_pipe and ref clocks from the pcie nodes
>  * dropped the child node from the phy nodes, like Johan suggested,
>    and updated to use the sc8280xp binding scheme
>  * changed "pcie_1_nocsr_com_phy_reset" 2nd reset name of pcie1_phy
>    to "nocsr"
>  * reordered all pcie nodes properties to look similar to the ones
>    from sc8280xp
> 
> [...]

Applied, thanks!

[1/2] arm64: dts: qcom: sm8550: Add PCIe PHYs and controllers nodes
      commit: 7d1158c984d37e79ab8bb55ab152a0b35566cb89
[2/2] arm64: dts: qcom: sm8550-mtp: Add PCIe PHYs and controllers nodes
      commit: 1eeef306b5d80494cdb149f058013c3ab43984b4

Best regards,
-- 
Bjorn Andersson <andersson@kernel.org>

Re: [PATCH v2 0/2] arm64: dts: qcom: sm8550: Add PCIe HC and PHY support

[Johan Hovold]

On Wed, Jan 18, 2023 at 05:55:31PM -0600, Bjorn Andersson wrote:
> On Thu, 19 Jan 2023 01:05:24 +0200, Abel Vesa wrote:
> > This patchset adds PCIe controllers and PHYs support to SM8550 platform
> > and enables them on the MTP board.
> > 
> > The v1 was here:
> > https://lore.kernel.org/all/20221116130430.2812173-1-abel.vesa@linaro.org/
> > 
> > Changes since v1:
> >  * ordered pcie related nodes alphabetically in MTP dts
> >  * dropped the pipe_mux, phy_pipe and ref clocks from the pcie nodes
> >  * dropped the child node from the phy nodes, like Johan suggested,
> >    and updated to use the sc8280xp binding scheme
> >  * changed "pcie_1_nocsr_com_phy_reset" 2nd reset name of pcie1_phy
> >    to "nocsr"
> >  * reordered all pcie nodes properties to look similar to the ones
> >    from sc8280xp
> > 
> > [...]
> 
> Applied, thanks!
> 
> [1/2] arm64: dts: qcom: sm8550: Add PCIe PHYs and controllers nodes
>       commit: 7d1158c984d37e79ab8bb55ab152a0b35566cb89
> [2/2] arm64: dts: qcom: sm8550-mtp: Add PCIe PHYs and controllers nodes
>       commit: 1eeef306b5d80494cdb149f058013c3ab43984b4

I believe there were still some changes needed to the controller
and PHY bindings so this should not have been merged.

	https://lore.kernel.org/all/Y8fuUI4xaNkADkWl@hovoldconsulting.com/
	https://lore.kernel.org/lkml/Y8giHJMtPu4wTlmA@hovoldconsulting.com/

Perhaps in the future you can send the dts changes along with the (PHY)
driver changes so that they can be kept in lock-step and avoid this.

Johan

Re: [PATCH v2 0/2] arm64: dts: qcom: sm8550: Add PCIe HC and PHY support

[Abel Vesa]

On 23-01-19 08:33:20, Johan Hovold wrote:
> On Wed, Jan 18, 2023 at 05:55:31PM -0600, Bjorn Andersson wrote:
> > On Thu, 19 Jan 2023 01:05:24 +0200, Abel Vesa wrote:
> > > This patchset adds PCIe controllers and PHYs support to SM8550 platform
> > > and enables them on the MTP board.
> > > 
> > > The v1 was here:
> > > https://lore.kernel.org/all/20221116130430.2812173-1-abel.vesa@linaro.org/
> > > 
> > > Changes since v1:
> > >  * ordered pcie related nodes alphabetically in MTP dts
> > >  * dropped the pipe_mux, phy_pipe and ref clocks from the pcie nodes
> > >  * dropped the child node from the phy nodes, like Johan suggested,
> > >    and updated to use the sc8280xp binding scheme
> > >  * changed "pcie_1_nocsr_com_phy_reset" 2nd reset name of pcie1_phy
> > >    to "nocsr"
> > >  * reordered all pcie nodes properties to look similar to the ones
> > >    from sc8280xp
> > > 
> > > [...]
> > 
> > Applied, thanks!
> > 
> > [1/2] arm64: dts: qcom: sm8550: Add PCIe PHYs and controllers nodes
> >       commit: 7d1158c984d37e79ab8bb55ab152a0b35566cb89
> > [2/2] arm64: dts: qcom: sm8550-mtp: Add PCIe PHYs and controllers nodes
> >       commit: 1eeef306b5d80494cdb149f058013c3ab43984b4
> 
> I believe there were still some changes needed to the controller
> and PHY bindings so this should not have been merged.
> 
> 	https://lore.kernel.org/all/Y8fuUI4xaNkADkWl@hovoldconsulting.com/
> 	https://lore.kernel.org/lkml/Y8giHJMtPu4wTlmA@hovoldconsulting.com/
> 
> Perhaps in the future you can send the dts changes along with the (PHY)
> driver changes so that they can be kept in lock-step and avoid this.

Well, that is a bit hard to do, because phy patches are based on
linux-phy/next, while dtsi patches are based on Bjorn's tree which,
so ...

> 
> Johan

Re: [PATCH v2 0/2] arm64: dts: qcom: sm8550: Add PCIe HC and PHY support

[Krzysztof Kozlowski]

On 19/01/2023 13:09, Abel Vesa wrote:
> On 23-01-19 08:33:20, Johan Hovold wrote:
>> On Wed, Jan 18, 2023 at 05:55:31PM -0600, Bjorn Andersson wrote:
>>> On Thu, 19 Jan 2023 01:05:24 +0200, Abel Vesa wrote:
>>>> This patchset adds PCIe controllers and PHYs support to SM8550 platform
>>>> and enables them on the MTP board.
>>>>
>>>> The v1 was here:
>>>> https://lore.kernel.org/all/20221116130430.2812173-1-abel.vesa@linaro.org/
>>>>
>>>> Changes since v1:
>>>>  * ordered pcie related nodes alphabetically in MTP dts
>>>>  * dropped the pipe_mux, phy_pipe and ref clocks from the pcie nodes
>>>>  * dropped the child node from the phy nodes, like Johan suggested,
>>>>    and updated to use the sc8280xp binding scheme
>>>>  * changed "pcie_1_nocsr_com_phy_reset" 2nd reset name of pcie1_phy
>>>>    to "nocsr"
>>>>  * reordered all pcie nodes properties to look similar to the ones
>>>>    from sc8280xp
>>>>
>>>> [...]
>>>
>>> Applied, thanks!
>>>
>>> [1/2] arm64: dts: qcom: sm8550: Add PCIe PHYs and controllers nodes
>>>       commit: 7d1158c984d37e79ab8bb55ab152a0b35566cb89
>>> [2/2] arm64: dts: qcom: sm8550-mtp: Add PCIe PHYs and controllers nodes
>>>       commit: 1eeef306b5d80494cdb149f058013c3ab43984b4
>>
>> I believe there were still some changes needed to the controller
>> and PHY bindings so this should not have been merged.
>>
>> 	https://lore.kernel.org/all/Y8fuUI4xaNkADkWl@hovoldconsulting.com/
>> 	https://lore.kernel.org/lkml/Y8giHJMtPu4wTlmA@hovoldconsulting.com/
>>
>> Perhaps in the future you can send the dts changes along with the (PHY)
>> driver changes so that they can be kept in lock-step and avoid this.
> 
> Well, that is a bit hard to do, because phy patches are based on
> linux-phy/next, while dtsi patches are based on Bjorn's tree which,
> so ...

... which we long time solved by basing your patches on linux-next.
That's the only way for inter-tree patchsets to be properly based.

Best regards,
Krzysztof

Re: [PATCH v2 0/2] arm64: dts: qcom: sm8550: Add PCIe HC and PHY support

[Abel Vesa]

On 23-01-19 13:29:38, Krzysztof Kozlowski wrote:
> On 19/01/2023 13:09, Abel Vesa wrote:
> > On 23-01-19 08:33:20, Johan Hovold wrote:
> >> On Wed, Jan 18, 2023 at 05:55:31PM -0600, Bjorn Andersson wrote:
> >>> On Thu, 19 Jan 2023 01:05:24 +0200, Abel Vesa wrote:
> >>>> This patchset adds PCIe controllers and PHYs support to SM8550 platform
> >>>> and enables them on the MTP board.
> >>>>
> >>>> The v1 was here:
> >>>> https://lore.kernel.org/all/20221116130430.2812173-1-abel.vesa@linaro.org/
> >>>>
> >>>> Changes since v1:
> >>>>  * ordered pcie related nodes alphabetically in MTP dts
> >>>>  * dropped the pipe_mux, phy_pipe and ref clocks from the pcie nodes
> >>>>  * dropped the child node from the phy nodes, like Johan suggested,
> >>>>    and updated to use the sc8280xp binding scheme
> >>>>  * changed "pcie_1_nocsr_com_phy_reset" 2nd reset name of pcie1_phy
> >>>>    to "nocsr"
> >>>>  * reordered all pcie nodes properties to look similar to the ones
> >>>>    from sc8280xp
> >>>>
> >>>> [...]
> >>>
> >>> Applied, thanks!
> >>>
> >>> [1/2] arm64: dts: qcom: sm8550: Add PCIe PHYs and controllers nodes
> >>>       commit: 7d1158c984d37e79ab8bb55ab152a0b35566cb89
> >>> [2/2] arm64: dts: qcom: sm8550-mtp: Add PCIe PHYs and controllers nodes
> >>>       commit: 1eeef306b5d80494cdb149f058013c3ab43984b4
> >>
> >> I believe there were still some changes needed to the controller
> >> and PHY bindings so this should not have been merged.
> >>
> >> 	https://lore.kernel.org/all/Y8fuUI4xaNkADkWl@hovoldconsulting.com/
> >> 	https://lore.kernel.org/lkml/Y8giHJMtPu4wTlmA@hovoldconsulting.com/
> >>
> >> Perhaps in the future you can send the dts changes along with the (PHY)
> >> driver changes so that they can be kept in lock-step and avoid this.
> > 
> > Well, that is a bit hard to do, because phy patches are based on
> > linux-phy/next, while dtsi patches are based on Bjorn's tree which,
> > so ...
> 
> ... which we long time solved by basing your patches on linux-next.
> That's the only way for inter-tree patchsets to be properly based.

Yeah, I just realized that out after I sent the reply :-)

Will send a single patchset which adds both the controller changes,
the phy changes and the dts/i changes (including all related bindings
updates).

> 
> Best regards,
> Krzysztof
>