From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D8BBCC677F1 for ; Thu, 19 Jan 2023 00:46:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229845AbjASAp6 (ORCPT ); Wed, 18 Jan 2023 19:45:58 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54456 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229804AbjASApy (ORCPT ); Wed, 18 Jan 2023 19:45:54 -0500 Received: from mail-wm1-x32b.google.com (mail-wm1-x32b.google.com [IPv6:2a00:1450:4864:20::32b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5AF38599A5 for ; Wed, 18 Jan 2023 16:45:46 -0800 (PST) Received: by mail-wm1-x32b.google.com with SMTP id o17-20020a05600c511100b003db021ef437so159016wms.4 for ; Wed, 18 Jan 2023 16:45:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=a8/xWpAcDkdgk1icsRNqf+wdsO/KBgKaXhirqdyPof8=; b=PX2zPyy4OThD62kGdMrKNdNU6o19gb7kSaj385ACxjkur+j6G+n61iTZbXPmVSB7ol DWkQ2cKNH/KGyluXgLi8WXtIiNeHDJj5UhsxnN3axaFcbrD0ORaZuw5GtZbLdRphq1cx MqVuXJUebfu8PBC3EmXxQCMQRgWi7NCY0+YgRjPgjBgNlS2Whxvr1saaK9vE0eo4UXmD HhqENA0keJgq2TWw45ZGXzuTY+shfBYTtGuAhNAhIBtMTn1Eno+FyNOY9IR//lNWHefa KpGYXdPWtfGKiJeNfzudoLU0MQL5BPv3cm8MN4gg8THS0sqiRl3u2yR24/o4Xsbh5dgI BOZw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=a8/xWpAcDkdgk1icsRNqf+wdsO/KBgKaXhirqdyPof8=; b=Jud/Rfka7WqvPNbMmVV5Cy9WpOJ82GOygLwAlCDhcFh9WuaL3ZPsYS/iYLUxKBXrDe oZRDI/3csSN9o2CxohOqU8NpvuezBVl/pCApNwBIEZa5305RdGVIp464693iGUNfnilD VSKEB7Bd/qQxd/r6QbTgmbTmOQi9R0uGXV0eBL409YB9HnbUZzu4Zn+3FfUGPKxOnmi0 LtkQAGjrdM4760yekKuBGN3pymwmP2nr3pQNdNEZjhOlh56lO6xVLCvybPq48JujyYio QHIlpqjo5Yn0jcaTvryeGdJulQwVZPRmJgZCI6Grs/tQ+oTpefNCO2ZsjaTJLRY3FHgJ ztRA== X-Gm-Message-State: AFqh2kpfFHfzcPwqFzUnlLLqYkCoAEnHq6oeGHPGQgS1Aol14y/4m9G0 YuNqT6n4G4bcNKc8oZKM3x+zqr1rq34IwCuS X-Google-Smtp-Source: AMrXdXt0bWMUbnrJHitjeMypwWzIQZ+o5ID7W61/9MAkq7Q2Ir/55SdTG56nRPsa+3VD9nIeaMNH4A== X-Received: by 2002:a05:600c:4f51:b0:3d2:139e:f64f with SMTP id m17-20020a05600c4f5100b003d2139ef64fmr8656425wmq.40.1674089144947; Wed, 18 Jan 2023 16:45:44 -0800 (PST) Received: from hackbox.lan ([94.52.112.99]) by smtp.gmail.com with ESMTPSA id m16-20020a05600c3b1000b003dafadd2f77sm3870491wms.1.2023.01.18.16.45.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Jan 2023 16:45:44 -0800 (PST) From: Abel Vesa To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Linux Kernel Mailing List Subject: [PATCH v2 1/2] arm64: dts: qcom: sm8550: Add USB PHYs and controller nodes Date: Thu, 19 Jan 2023 02:45:32 +0200 Message-Id: <20230119004533.1869870-2-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230119004533.1869870-1-abel.vesa@linaro.org> References: <20230119004533.1869870-1-abel.vesa@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add USB host controller and PHY nodes. Signed-off-by: Abel Vesa --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 92 +++++++++++++++++++++++++++- 1 file changed, 91 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index a78068cbf95f..bdbf5bf8aa7d 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -13,6 +13,7 @@ #include #include #include +#include #include / { @@ -652,7 +653,7 @@ gcc: clock-controller@100000 { <&ufs_mem_phy 0>, <&ufs_mem_phy 1>, <&ufs_mem_phy 2>, - <0>; + <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; }; ipcc: mailbox@408000 { @@ -1934,6 +1935,95 @@ opp-202000000 { }; }; + usb_1_hsphy: phy@88e3000 { + compatible = "qcom,sm8550-snps-eusb2-phy"; + reg = <0x0 0x088e3000 0x0 0x154>; + #phy-cells = <0>; + + clocks = <&tcsr TCSR_USB2_CLKREF_EN>; + clock-names = "ref"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + + status = "disabled"; + }; + + usb_dp_qmpphy: phy@88e8000 { + compatible = "qcom,sm8550-qmp-usb3-dp-phy"; + reg = <0x0 0x088e8000 0x0 0x3000>; + + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names = "aux", "ref", "com_aux", "usb3_pipe"; + + power-domains = <&gcc USB3_PHY_GDSC>; + + resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, + <&gcc GCC_USB3_PHY_PRIM_BCR>; + reset-names = "phy", "common"; + + #clock-cells = <1>; + #phy-cells = <1>; + + status = "disabled"; + }; + + usb_1: usb@a6f8800 { + compatible = "qcom,sm8550-dwc3", "qcom,dwc3"; + reg = <0x0 0x0a6f8800 0x0 0x400>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&tcsr TCSR_USB3_CLKREF_EN>; + clock-names = "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi", + "xo"; + + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates = <19200000>, <200000000>; + + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 15 IRQ_TYPE_EDGE_RISING>, + <&pdc 14 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "hs_phy_irq", + "ss_phy_irq", + "dm_hs_phy_irq", + "dp_hs_phy_irq"; + + power-domains = <&gcc USB30_PRIM_GDSC>; + required-opps = <&rpmhpd_opp_nom>; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + + status = "disabled"; + + usb_1_dwc3: usb@a600000 { + compatible = "snps,dwc3"; + reg = <0x0 0x0a600000 0x0 0xcd00>; + interrupts = ; + iommus = <&apps_smmu 0x40 0x0>; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,usb3_lpm_capable; + phys = <&usb_1_hsphy>, + <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>; + phy-names = "usb2-phy", "usb3-phy"; + }; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sm8550-pdc", "qcom,pdc"; reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; -- 2.34.1