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From: Rodrigo Vivi <rodrigo.vivi@intel.com>
To: intel-xe@lists.freedesktop.org,
	maarten.lankhorst@linux.intel.com, philippe.lecluse@intel.com,
	mchehab@kernel.org
Cc: Francois Dugast <francois.dugast@intel.com>,
	Rodrigo Vivi <rodrigo.vivi@intel.com>
Subject: [Intel-xe] [PATCH 20/20] drm/xe/guc_pc: Fix Meteor Lake registers.
Date: Fri, 20 Jan 2023 15:44:26 -0500	[thread overview]
Message-ID: <20230120204426.68104-21-rodrigo.vivi@intel.com> (raw)
In-Reply-To: <20230120204426.68104-1-rodrigo.vivi@intel.com>

When adding the frequency management, Meteor Lake platform
was left behind. Handling it properly now.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
Cc: Francois Dugast <francois.dugast@intel.com>
---
 drivers/gpu/drm/xe/xe_guc_pc.c | 70 ++++++++++++++++++++++++++++++++--
 1 file changed, 66 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_guc_pc.c b/drivers/gpu/drm/xe/xe_guc_pc.c
index 506b9cb3f14c..bf3dff9e0c2b 100644
--- a/drivers/gpu/drm/xe/xe_guc_pc.c
+++ b/drivers/gpu/drm/xe/xe_guc_pc.c
@@ -37,6 +37,9 @@
 #define GEN12_RPSTAT1		_MMIO(0x1381b4)
 #define   GEN12_CAGF_MASK	REG_GENMASK(19, 11)
 
+#define MTL_MIRROR_TARGET_WP1	_MMIO(0xc60)
+#define   MTL_CAGF_MASK		REG_GENMASK(8, 0)
+
 #define GT_FREQUENCY_MULTIPLIER	50
 #define GEN9_FREQ_SCALER	3
 
@@ -311,7 +314,20 @@ static int pc_set_max_freq(struct xe_guc_pc *pc, u32 freq)
 				   freq);
 }
 
-static void pc_update_rp_values(struct xe_guc_pc *pc)
+static void mtl_update_rpe_value(struct xe_guc_pc *pc)
+{
+	struct xe_gt *gt = pc_to_gt(pc);
+	u32 reg;
+
+	if (xe_gt_is_media_type(gt))
+		reg = xe_mmio_read32(gt, MTL_MPE_FREQUENCY.reg);
+	else
+		reg = xe_mmio_read32(gt, MTL_GT_RPE_FREQUENCY.reg);
+
+	pc->rpe_freq = REG_FIELD_GET(MTL_RPE_MASK, reg) * GT_FREQUENCY_MULTIPLIER;
+}
+
+static void tgl_update_rpe_value(struct xe_guc_pc *pc)
 {
 	struct xe_gt *gt = pc_to_gt(pc);
 	struct xe_device *xe = gt_to_xe(gt);
@@ -328,6 +344,17 @@ static void pc_update_rp_values(struct xe_guc_pc *pc)
 		reg = xe_mmio_read32(gt, GEN10_FREQ_INFO_REC.reg);
 
 	pc->rpe_freq = REG_FIELD_GET(RPE_MASK, reg) * GT_FREQUENCY_MULTIPLIER;
+}
+
+static void pc_update_rp_values(struct xe_guc_pc *pc)
+{
+	struct xe_gt *gt = pc_to_gt(pc);
+	struct xe_device *xe = gt_to_xe(gt);
+
+	if (xe->info.platform == XE_METEORLAKE)
+		mtl_update_rpe_value(pc);
+	else
+		tgl_update_rpe_value(pc);
 
 	/*
 	 * RPe is decided at runtime by PCODE. In the rare case where that's
@@ -342,6 +369,7 @@ static ssize_t freq_act_show(struct device *dev,
 {
 	struct kobject *kobj = &dev->kobj;
 	struct xe_gt *gt = kobj_to_gt(kobj);
+	struct xe_device *xe = gt_to_xe(gt);
 	u32 freq;
 	ssize_t ret;
 
@@ -354,10 +382,17 @@ static ssize_t freq_act_show(struct device *dev,
 		return ret;
 
 	xe_device_mem_access_get(gt_to_xe(gt));
-	freq = xe_mmio_read32(gt, GEN12_RPSTAT1.reg);
+
+	if (xe->info.platform == XE_METEORLAKE) {
+		freq = xe_mmio_read32(gt, MTL_MIRROR_TARGET_WP1.reg);
+		freq = REG_FIELD_GET(MTL_CAGF_MASK, freq);
+	} else {
+		freq = xe_mmio_read32(gt, GEN12_RPSTAT1.reg);
+		freq = REG_FIELD_GET(GEN12_CAGF_MASK, freq);
+	}
+
 	xe_device_mem_access_put(gt_to_xe(gt));
 
-	freq = REG_FIELD_GET(GEN12_CAGF_MASK, freq);
 	ret = sysfs_emit(buf, "%d\n", decode_freq(freq));
 
 	XE_WARN_ON(xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL));
@@ -606,7 +641,24 @@ static const struct attribute *pc_attrs[] = {
 	NULL
 };
 
-static void pc_init_fused_rp_values(struct xe_guc_pc *pc)
+static void mtl_init_fused_rp_values(struct xe_guc_pc *pc)
+{
+	struct xe_gt *gt = pc_to_gt(pc);
+	u32 reg;
+
+	xe_device_assert_mem_access(pc_to_xe(pc));
+
+	if (xe_gt_is_media_type(gt))
+		reg = xe_mmio_read32(gt, MTL_MEDIAP_STATE_CAP.reg);
+	else
+		reg = xe_mmio_read32(gt, MTL_RP_STATE_CAP.reg);
+	pc->rp0_freq = REG_FIELD_GET(MTL_RP0_CAP_MASK, reg) *
+		GT_FREQUENCY_MULTIPLIER;
+	pc->rpn_freq = REG_FIELD_GET(MTL_RPN_CAP_MASK, reg) *
+		GT_FREQUENCY_MULTIPLIER;
+}
+
+static void tgl_init_fused_rp_values(struct xe_guc_pc *pc)
 {
 	struct xe_gt *gt = pc_to_gt(pc);
 	struct xe_device *xe = gt_to_xe(gt);
@@ -622,6 +674,16 @@ static void pc_init_fused_rp_values(struct xe_guc_pc *pc)
 	pc->rpn_freq = REG_FIELD_GET(RPN_MASK, reg) * GT_FREQUENCY_MULTIPLIER;
 }
 
+static void pc_init_fused_rp_values(struct xe_guc_pc *pc)
+{
+	struct xe_gt *gt = pc_to_gt(pc);
+	struct xe_device *xe = gt_to_xe(gt);
+
+	if (xe->info.platform == XE_METEORLAKE)
+		mtl_init_fused_rp_values(pc);
+	else
+		tgl_init_fused_rp_values(pc);
+}
 static int pc_adjust_freq_bounds(struct xe_guc_pc *pc)
 {
 	int ret;
-- 
2.39.0



      parent reply	other threads:[~2023-01-20 20:44 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-01-20 20:44 [Intel-xe] [PATCH 00/20] Catching up - round 2 Rodrigo Vivi
2023-01-20 20:44 ` [Intel-xe] [PATCH 01/20] drm/xe/migrate: Update emit_pte to cope with a size level than 4k Rodrigo Vivi
2023-01-20 20:44 ` [Intel-xe] [PATCH 02/20] drm/xe/fbc: set compressed_fb to NULL on error Rodrigo Vivi
2023-01-31 19:20   ` Rodrigo Vivi
2023-01-20 20:44 ` [Intel-xe] [PATCH 03/20] drm/xe/pcode: fix pcode error check Rodrigo Vivi
2023-01-20 20:44 ` [Intel-xe] [PATCH 04/20] drm/xe: fix xe_mmio_total_vram_size Rodrigo Vivi
2023-01-20 20:44 ` [Intel-xe] [PATCH 05/20] drm/xe/ggtt: Use BIT_ULL() for 64bit Rodrigo Vivi
2023-01-20 20:44 ` [Intel-xe] [PATCH 06/20] drm/xe: Fix some log messages on 32b Rodrigo Vivi
2023-01-20 20:44 ` [Intel-xe] [PATCH 07/20] drm/xe/mmio: Use non-atomic writeq/readq variant for 32b Rodrigo Vivi
2023-01-20 20:44 ` [Intel-xe] [PATCH 08/20] drm/xe: Fix tracepoints on 32b Rodrigo Vivi
2023-01-20 20:44 ` [Intel-xe] [PATCH 09/20] drm/xe/gt: Fix min() with u32 and u64 Rodrigo Vivi
2023-01-20 20:44 ` [Intel-xe] [PATCH 10/20] drm/xe: Add documentation for mem_type Rodrigo Vivi
2023-01-20 20:44 ` [Intel-xe] [PATCH 11/20] drm/xe/ext: Dont call intel_display_power_is_enabled from irq install/remove Rodrigo Vivi
2023-01-20 20:44 ` [Intel-xe] [PATCH 12/20] ]65; 7002; 1cdrm/xe: Add min config for kunit integration ARCH=um Rodrigo Vivi
2023-01-20 22:58   ` Mauro Carvalho Chehab
2023-01-24 23:13   ` Lucas De Marchi
2023-01-31 19:30     ` Rodrigo Vivi
2023-01-31 19:23   ` Rodrigo Vivi
2023-01-20 20:44 ` [Intel-xe] [PATCH 13/20] drm/xe/Kconfig.debug: select DEBUG_FS for KUnit runs Rodrigo Vivi
2023-01-20 20:44 ` [Intel-xe] [PATCH 14/20] drm/xe: KUnit tests depend on CONFIG_DRM_FBDEV_EMULATION Rodrigo Vivi
2023-01-20 20:44 ` [Intel-xe] [PATCH 15/20] drm/xe: fix XE_DISPLAY dependency on ACPI Rodrigo Vivi
2023-01-24 16:02   ` Lecluse, Philippe
2023-01-20 20:44 ` [Intel-xe] [PATCH 16/20] drm/xe: allow building XE_DISPLAY without ACPI Rodrigo Vivi
2023-01-20 20:44 ` [Intel-xe] [PATCH 17/20] drm/xe: fix DRM_FBDEV_EMULATION dependencies Rodrigo Vivi
2023-01-20 20:44 ` [Intel-xe] [PATCH 18/20] drm/xe/gt: Enable interrupt while initializing root gt Rodrigo Vivi
2023-01-20 20:44 ` [Intel-xe] [PATCH 19/20] drm/xe: Fix Meteor Lake rsa issue on guc loading Rodrigo Vivi
2023-01-20 20:44 ` Rodrigo Vivi [this message]

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