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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DS1PEPF0000E648.mail.protection.outlook.com (10.167.18.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6043.10 via Frontend Transport; Tue, 24 Jan 2023 21:26:25 +0000 Received: from platform-dev1.pensando.io (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Tue, 24 Jan 2023 15:26:21 -0600 From: Brad Larson To: CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: Re: [PATCH v9 04/15] dt-bindings: spi: dw: Add AMD Pensando Elba SoC SPI Controller bindings Date: Tue, 24 Jan 2023 13:26:15 -0800 Message-ID: <20230124212615.26080-1-blarson@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <84233b60-2468-4be9-7aa7-bdd296fd96e8@linaro.org> References: <84233b60-2468-4be9-7aa7-bdd296fd96e8@linaro.org> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF0000E648:EE_|CH3PR12MB7667:EE_ X-MS-Office365-Filtering-Correlation-Id: c3223926-b8d4-489e-ae88-08dafe51a5eb X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Jan 2023 21:26:25.5057 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c3223926-b8d4-489e-ae88-08dafe51a5eb X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0000E648.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB7667 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 24/01/2023 7:55 UTC, Krzysztof Kozlowski wrote: >On 24/01/2023 02:57, Brad Larson wrote: >> On 19/01/2023 7:55 UTC, Krzysztof Kozlowski wrote: >>> On 19/01/2023 04:51, Brad Larson wrote: >>>> The AMD Pensando Elba SoC has integrated the DW APB SPI Controller >>>> >> ... >>>> .../devicetree/bindings/spi/snps,dw-apb-ssi.yaml | 14 ++++++++++++++ >>>> 1 file changed, 14 insertions(+) >>>> >>>> diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml >>>> index d33b72fabc5d..96b072835de0 100644 >>>> --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml >>>> +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml >>>> @@ -37,6 +37,18 @@ allOf: >>>> else: >>>> required: >>>> - interrupts >>>> + - if: >>>> + properties: >>>> + compatible: >>>> + contains: >>>> + const: amd,pensando-elba-spi >>>> + then: >>>> + properties: >>>> + amd,pensando-elba-syscon: >>>> + $ref: /schemas/types.yaml#/definitions/phandle-array >>>> + description: AMD Pensando Elba SoC system controller >>> >>> And nothing here - neither in commit msg nor here - explains why do you >>> need it and what is it for. >> >> Adding property amd,pensando-elba-syscon was a result of this thread: >> https://lore.kernel.org/lkml/20220621101159.stvan53rvr6qugna@mobilestation/ >> > > But it is not in the code. The code should tell what the property does, > what is its purpose, how it is used etc. Your property description > basically copies the name without giving any new information. Yes, I looked past the description, thanks. See below the updated description and added amd,pensando-elba-syscon definition to top level properties. The property is added to the end as I see partial alphabetical ordering. --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml @@ -37,6 +37,17 @@ allOf: else: required: - interrupts + - if: + properties: + compatible: + contains: + const: amd,pensando-elba-spi + then: + required: + - amd,pensando-elba-syscon + else: + properties: + amd,pensando-elba-syscon: false properties: compatible: @@ -63,6 +74,8 @@ properties: const: intel,keembay-ssi - description: Intel Thunder Bay SPI Controller const: intel,thunderbay-ssi + - description: AMD Pensando Elba SoC SPI Controller + const: amd,pensando-elba-spi - description: Baikal-T1 SPI Controller const: baikal,bt1-ssi - description: Baikal-T1 System Boot SPI Controller @@ -136,6 +149,12 @@ properties: of the designware controller, and the upper limit is also subject to controller configuration. + amd,pensando-elba-syscon: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: | + Block address to control four spi chip-selects. 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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 24/01/2023 7:55 UTC, Krzysztof Kozlowski wrote: >On 24/01/2023 02:57, Brad Larson wrote: >> On 19/01/2023 7:55 UTC, Krzysztof Kozlowski wrote: >>> On 19/01/2023 04:51, Brad Larson wrote: >>>> The AMD Pensando Elba SoC has integrated the DW APB SPI Controller >>>> >> ... >>>> .../devicetree/bindings/spi/snps,dw-apb-ssi.yaml | 14 ++++++++++++++ >>>> 1 file changed, 14 insertions(+) >>>> >>>> diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml >>>> index d33b72fabc5d..96b072835de0 100644 >>>> --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml >>>> +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml >>>> @@ -37,6 +37,18 @@ allOf: >>>> else: >>>> required: >>>> - interrupts >>>> + - if: >>>> + properties: >>>> + compatible: >>>> + contains: >>>> + const: amd,pensando-elba-spi >>>> + then: >>>> + properties: >>>> + amd,pensando-elba-syscon: >>>> + $ref: /schemas/types.yaml#/definitions/phandle-array >>>> + description: AMD Pensando Elba SoC system controller >>> >>> And nothing here - neither in commit msg nor here - explains why do you >>> need it and what is it for. >> >> Adding property amd,pensando-elba-syscon was a result of this thread: >> https://lore.kernel.org/lkml/20220621101159.stvan53rvr6qugna@mobilestation/ >> > > But it is not in the code. The code should tell what the property does, > what is its purpose, how it is used etc. Your property description > basically copies the name without giving any new information. Yes, I looked past the description, thanks. See below the updated description and added amd,pensando-elba-syscon definition to top level properties. The property is added to the end as I see partial alphabetical ordering. --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml @@ -37,6 +37,17 @@ allOf: else: required: - interrupts + - if: + properties: + compatible: + contains: + const: amd,pensando-elba-spi + then: + required: + - amd,pensando-elba-syscon + else: + properties: + amd,pensando-elba-syscon: false properties: compatible: @@ -63,6 +74,8 @@ properties: const: intel,keembay-ssi - description: Intel Thunder Bay SPI Controller const: intel,thunderbay-ssi + - description: AMD Pensando Elba SoC SPI Controller + const: amd,pensando-elba-spi - description: Baikal-T1 SPI Controller const: baikal,bt1-ssi - description: Baikal-T1 System Boot SPI Controller @@ -136,6 +149,12 @@ properties: of the designware controller, and the upper limit is also subject to controller configuration. + amd,pensando-elba-syscon: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: | + Block address to control four spi chip-selects. The Elba SoC + does not use ssi. + patternProperties: "^.*@[0-9a-f]+$": type: object Regards, Brad _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel