From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EC5D9C54E94 for ; Wed, 25 Jan 2023 22:30:43 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 96FF5856E7; Wed, 25 Jan 2023 23:29:56 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=edgeble.ai Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=edgeble-ai.20210112.gappssmtp.com header.i=@edgeble-ai.20210112.gappssmtp.com header.b="BuRpK7E2"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 75371856EB; Wed, 25 Jan 2023 23:28:51 +0100 (CET) Received: from mail-pg1-x531.google.com (mail-pg1-x531.google.com [IPv6:2607:f8b0:4864:20::531]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id C5056856DD for ; Wed, 25 Jan 2023 23:28:18 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=edgeble.ai Authentication-Results: phobos.denx.de; spf=none smtp.mailfrom=jagan@edgeble.ai Received: by mail-pg1-x531.google.com with SMTP id 36so14390979pgp.10 for ; Wed, 25 Jan 2023 14:28:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=edgeble-ai.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BFkRYfn69U/CdVy1YfYIwLxF3VnRLQ0O2n+CzI6nar0=; b=BuRpK7E23jeHQLe9ZNxGPXJmch+I1Y9FWew7B+6+8EEfSyA98/bGyRBWAYicp1i7Ra lU9QmN3h8ynia3iWXkd+eJzbxwbjHBbGcw2+1Ig2yDKAYiKU9BIO0WqYnZXwuuuzH1U4 v6WfQmhcbllOtR7CxOjsRqIEmigZpQwEXV+yg+8rnZ9dIVNWKXPdSkEuoMiaqvMOpK+1 QQNAudPDFIXS8LMFtK6XZ+Cl++hCRIlMk8NVxwn98Xchc2RXQR2xOFmRh0zgrrYBqPep xC7kCQkaX6hpy1qSpOzd/Y7+PRj05b01/ghBkX9pXpVPxr/0ezd7eh3RJ3VbkfvUQhqw BJdw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BFkRYfn69U/CdVy1YfYIwLxF3VnRLQ0O2n+CzI6nar0=; b=d4F75SKXaNf6DWSYh1Oip1r5YXLg8lxpHP9UEyb4z5wQwnT1Lx7LRIciXKhFyOwEIL j4Mbd1q7UH1vn83ImExDObwVssekq5mlSzQ9ChOYUU+pJZBjk9o0ggttgx0vgi6W1n7f xgOuCM5WUrmI2nFUHxJmf4Q1SxM4x8RUB+8jZ1AyVSNpcpkgD4xqJfYP5psFcH2qi4BB j7xzHaIPpw6kTS+XAY8dAnqms5CMGeoRcGjoJxIzV+2xUjdpNvh8stWLcZ791bmVp+pc 4X97raKgsU9NHa+DQGE8kPzTEsO4Kdn54A7+jU3RUsgjkW67Mrzcb5EcQafGqae7X8N2 8CKg== X-Gm-Message-State: AFqh2kpXTDEDaWpxpK5jFTOyIKX6p/ERNC5Zt4kTzhd+tcJiHka75riP yttkLoJbDHVL+qcY3Pt7g1TTNg== X-Google-Smtp-Source: AMrXdXto4dZzzcRwEHJx9cGgM9v0Os8/hwXlpGyqoVPB9WWQAX05f6Sj55Im1mJj2raHRSpq5h5fYg== X-Received: by 2002:a05:6a00:301b:b0:586:9ba7:530e with SMTP id ay27-20020a056a00301b00b005869ba7530emr35888347pfb.31.1674685697093; Wed, 25 Jan 2023 14:28:17 -0800 (PST) Received: from localhost.localdomain ([2405:201:c00a:a238:3cb1:2156:ef87:8af5]) by smtp.gmail.com with ESMTPSA id u26-20020a62d45a000000b0058bb0b8750csm4134647pfl.88.2023.01.25.14.28.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Jan 2023 14:28:16 -0800 (PST) From: Jagan Teki To: Kever Yang , Simon Glass , Philipp Tomsich , fatorangecat@189.cn Cc: u-boot@lists.denx.de, Jagan Teki , Steven Liu , Joseph Chen Subject: [RFC PATCH 10/16] arm: rockchip: Add ioc header for rk3588 Date: Thu, 26 Jan 2023 03:57:35 +0530 Message-Id: <20230125222741.303259-11-jagan@edgeble.ai> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230125222741.303259-1-jagan@edgeble.ai> References: <20230125222741.303259-1-jagan@edgeble.ai> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Add IOC unit header include for rk3588. Signed-off-by: Steven Liu Signed-off-by: Joseph Chen Signed-off-by: Jagan Teki --- .../include/asm/arch-rockchip/ioc_rk3588.h | 102 ++++++++++++++++++ 1 file changed, 102 insertions(+) create mode 100644 arch/arm/include/asm/arch-rockchip/ioc_rk3588.h diff --git a/arch/arm/include/asm/arch-rockchip/ioc_rk3588.h b/arch/arm/include/asm/arch-rockchip/ioc_rk3588.h new file mode 100644 index 0000000000..2fd47b5d1c --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/ioc_rk3588.h @@ -0,0 +1,102 @@ +/* + * (C) Copyright 2021 Rockchip Electronics Co., Ltd. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _ASM_ARCH_IOC_RK3588_H +#define _ASM_ARCH_IOC_RK3588_H + +#include + +struct rk3588_bus_ioc { + uint32_t reserved0000[3]; /* Address Offset: 0x0000 */ + uint32_t gpio0b_iomux_sel_h; /* Address Offset: 0x000C */ + uint32_t gpio0c_iomux_sel_l; /* Address Offset: 0x0010 */ + uint32_t gpio0c_iomux_sel_h; /* Address Offset: 0x0014 */ + uint32_t gpio0d_iomux_sel_l; /* Address Offset: 0x0018 */ + uint32_t gpio0d_iomux_sel_h; /* Address Offset: 0x001C */ + uint32_t gpio1a_iomux_sel_l; /* Address Offset: 0x0020 */ + uint32_t gpio1a_iomux_sel_h; /* Address Offset: 0x0024 */ + uint32_t gpio1b_iomux_sel_l; /* Address Offset: 0x0028 */ + uint32_t gpio1b_iomux_sel_h; /* Address Offset: 0x002C */ + uint32_t gpio1c_iomux_sel_l; /* Address Offset: 0x0030 */ + uint32_t gpio1c_iomux_sel_h; /* Address Offset: 0x0034 */ + uint32_t gpio1d_iomux_sel_l; /* Address Offset: 0x0038 */ + uint32_t gpio1d_iomux_sel_h; /* Address Offset: 0x003C */ + uint32_t gpio2a_iomux_sel_l; /* Address Offset: 0x0040 */ + uint32_t gpio2a_iomux_sel_h; /* Address Offset: 0x0044 */ + uint32_t gpio2b_iomux_sel_l; /* Address Offset: 0x0048 */ + uint32_t gpio2b_iomux_sel_h; /* Address Offset: 0x004C */ + uint32_t gpio2c_iomux_sel_l; /* Address Offset: 0x0050 */ + uint32_t gpio2c_iomux_sel_h; /* Address Offset: 0x0054 */ + uint32_t gpio2d_iomux_sel_l; /* Address Offset: 0x0058 */ + uint32_t gpio2d_iomux_sel_h; /* Address Offset: 0x005C */ + uint32_t gpio3a_iomux_sel_l; /* Address Offset: 0x0060 */ + uint32_t gpio3a_iomux_sel_h; /* Address Offset: 0x0064 */ + uint32_t gpio3b_iomux_sel_l; /* Address Offset: 0x0068 */ + uint32_t gpio3b_iomux_sel_h; /* Address Offset: 0x006C */ + uint32_t gpio3c_iomux_sel_l; /* Address Offset: 0x0070 */ + uint32_t gpio3c_iomux_sel_h; /* Address Offset: 0x0074 */ + uint32_t gpio3d_iomux_sel_l; /* Address Offset: 0x0078 */ + uint32_t gpio3d_iomux_sel_h; /* Address Offset: 0x007C */ + uint32_t gpio4a_iomux_sel_l; /* Address Offset: 0x0080 */ + uint32_t gpio4a_iomux_sel_h; /* Address Offset: 0x0084 */ + uint32_t gpio4b_iomux_sel_l; /* Address Offset: 0x0088 */ + uint32_t gpio4b_iomux_sel_h; /* Address Offset: 0x008C */ + uint32_t gpio4c_iomux_sel_l; /* Address Offset: 0x0090 */ + uint32_t gpio4c_iomux_sel_h; /* Address Offset: 0x0094 */ + uint32_t gpio4d_iomux_sel_l; /* Address Offset: 0x0098 */ + uint32_t gpio4d_iomux_sel_h; /* Address Offset: 0x009C */ +}; +check_member(rk3588_bus_ioc, gpio4d_iomux_sel_h, 0x009C); + + +struct rk3588_pmu1_ioc { + uint32_t gpio0a_iomux_sel_l; /* Address Offset: 0x0000 */ + uint32_t gpio0a_iomux_sel_h; /* Address Offset: 0x0004 */ + uint32_t gpio0b_iomux_sel_l; /* Address Offset: 0x0008 */ + uint32_t reserved0012; /* Address Offset: 0x000C */ + uint32_t gpio0a_ds_l; /* Address Offset: 0x0010 */ + uint32_t gpio0a_ds_h; /* Address Offset: 0x0014 */ + uint32_t gpio0b_ds_l; /* Address Offset: 0x0018 */ + uint32_t reserved0028; /* Address Offset: 0x001C */ + uint32_t gpio0a_p; /* Address Offset: 0x0020 */ + uint32_t gpio0b_p; /* Address Offset: 0x0024 */ + uint32_t gpio0a_ie; /* Address Offset: 0x0028 */ + uint32_t gpio0b_ie; /* Address Offset: 0x002C */ + uint32_t gpio0a_smt; /* Address Offset: 0x0030 */ + uint32_t gpio0b_smt; /* Address Offset: 0x0034 */ + uint32_t gpio0a_pdis; /* Address Offset: 0x0038 */ + uint32_t gpio0b_pdis; /* Address Offset: 0x003C */ + uint32_t xin_con; /* Address Offset: 0x0040 */ +}; +check_member(rk3588_pmu1_ioc, xin_con, 0x0040); + +struct rk3588_pmu2_ioc { + uint32_t gpio0b_iomux_sel_h; /* Address Offset: 0x0000 */ + uint32_t gpio0c_iomux_sel_l; /* Address Offset: 0x0004 */ + uint32_t gpio0c_iomux_sel_h; /* Address Offset: 0x0008 */ + uint32_t gpio0d_iomux_sel_l; /* Address Offset: 0x000C */ + uint32_t gpio0d_iomux_sel_h; /* Address Offset: 0x0010 */ + uint32_t gpio0b_ds_h; /* Address Offset: 0x0014 */ + uint32_t gpio0c_ds_l; /* Address Offset: 0x0018 */ + uint32_t gpio0c_ds_h; /* Address Offset: 0x001C */ + uint32_t gpio0d_ds_l; /* Address Offset: 0x0020 */ + uint32_t gpio0d_ds_h; /* Address Offset: 0x0024 */ + uint32_t gpio0b_p; /* Address Offset: 0x0028 */ + uint32_t gpio0c_p; /* Address Offset: 0x002C */ + uint32_t gpio0d_p; /* Address Offset: 0x0030 */ + uint32_t gpio0b_ie; /* Address Offset: 0x0034 */ + uint32_t gpio0c_ie; /* Address Offset: 0x0038 */ + uint32_t gpio0d_ie; /* Address Offset: 0x003C */ + uint32_t gpio0b_smt; /* Address Offset: 0x0040 */ + uint32_t gpio0c_smt; /* Address Offset: 0x0044 */ + uint32_t gpio0d_smt; /* Address Offset: 0x0048 */ + uint32_t gpio0b_pdis; /* Address Offset: 0x004C */ + uint32_t gpio0c_pdis; /* Address Offset: 0x0050 */ + uint32_t gpio0d_pdis; /* Address Offset: 0x0054 */ +}; +check_member(rk3588_pmu2_ioc, gpio0d_pdis, 0x0054); + +#endif + -- 2.25.1