From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 45586C54E94 for ; Thu, 26 Jan 2023 11:09:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237172AbjAZLJf (ORCPT ); Thu, 26 Jan 2023 06:09:35 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55594 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237117AbjAZLJZ (ORCPT ); Thu, 26 Jan 2023 06:09:25 -0500 Received: from mout.perfora.net (mout.perfora.net [74.208.4.194]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A39A0410A0; Thu, 26 Jan 2023 03:09:23 -0800 (PST) Received: from toolbox.toradex.int ([31.10.206.125]) by mrelay.perfora.net (mreueus002 [74.208.5.2]) with ESMTPSA (Nemesis) id 0LdHBn-1ov36z12NF-00iR7n; Thu, 26 Jan 2023 12:09:08 +0100 From: Marcel Ziswiler To: devicetree@vger.kernel.org Cc: linux-imx@nxp.com, Liu Ying , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Joakim Zhang , Marcel Ziswiler , Fabio Estevam , Frank Li , Krzysztof Kozlowski , Max Krummenacher , Peng Fan , Pengutronix Kernel Team , Philippe Schenker , Rob Herring , Sascha Hauer , Shawn Guo Subject: [PATCH v5 05/10] arm64: dts: imx8qxp: add flexcan in adma Date: Thu, 26 Jan 2023 12:08:28 +0100 Message-Id: <20230126110833.264439-6-marcel@ziswiler.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20230126110833.264439-1-marcel@ziswiler.com> References: <20230126110833.264439-1-marcel@ziswiler.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Provags-ID: V03:K1:fQWw0GOX+nKPn6Z3NSaSeEwe1U943hr8DyyHXIPa/bsUYvsHEtr +pEppte+ECkpMC1zG1kBn3l6Vxt/Pe5brnOBmN965w9xJpJitFWj2KadZJzPaOrhYKGyTJz 3idB2HSgjvPPXDEWy7uEmcYFvI+Z2Txxyl2ibX4yn40XEve+Lba/uZzZaOtyf5ArQWd3d1P eBti9Pq4N6E5Q3zHTlUdQ== UI-OutboundReport: notjunk:1;M01:P0:ZGgyyNtw80Q=;2HZ8Ryrc35DTl3hfRogXBaLyA6U QgZbQZ0V/4oqkrmBXSPTETFDq13goaWXD7mGcaoFPya8YB/WpYvMAqJZesQCnzcLSEvUgc/a2 VL8YTfaXsPSsEn9a+KkUsV5rAhkvqEw6kuRbzcTsK0dSnfnxdxq4HNunPu6UsNGDfcSnVqVo/ 6HRT7FCDGvltL/7ItWRrQoD+VdXapfyjYzu54bzfbvlYJz5/CmqXNNC2vCFO1qjC+c3m0wg6A jHDaLBu+mU4Rpibh1bE13IfVzhsSF8njc8Naqw1ZUrdYdmclz2pchxzwIgWZcXFzxlfdlFEQ3 KYlAhnCB0UIYBh5+o+kTDYfEDS93+DIbgnF3Xa0QWI+tZiXcWM/YZkR2YtLl9q6iCUhV5VhyQ Hwyz50uGneX7jJZYDE/IChZoiTQsakQlz+HJRqZnc0V1NQpTFk6lBFYdES4iD5sppxnLMrcHW AT2qmRKxdxf3+MImnBAbZfCtdvuAi9mmXcUqpvpUh5FTPBOLq1Qz5kOifVK/ugGVnWtDKlZIh 0Ro4W/mqQmIKgG1M3CCLeVaj3TvX9FC3WLvaJrumhS6+dAloSNXd1Y1y2NReu8APprp0x3uPx mNwuY71LoYTBHpr+EgZJ1QTyfjBdRfZ2IRHEPKhT1yG/80aVSjvlo/Zutz6RjehyO0hyd8QCr M7cvxDEwjvrhxOSlvoFcHh1OKfGYg3C0oWgMpszUow== Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Joakim Zhang Add FlexCAN decive in adma subsystem. Signed-off-by: Joakim Zhang Signed-off-by: Marcel Ziswiler --- (no changes since v4) Changes in v4: - New patch combining the following downstream patches: commit e8fe3f57223a ("arm64: dts: imx8qxp: add FlexCAN in adma") commit 4e90361f1ed3 ("arm64: dts: imx8qxp: add multi-pd support for CAN1/2") commit 899f516e61f8 ("arm64: dts: imx8: dma: fully switched to new clk binding") commit 8a28ca15a058 ("arm64: dts: imx8qxp: drop multi-pd for CAN device") commit c493402197dd ("arm64: dts: imx8: update CAN fsl,clk-source and fsl,scu-index property") .../arm64/boot/dts/freescale/imx8-ss-dma.dtsi | 72 +++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi index 6ccf926b77a5..2dce8f2ee3ea 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi @@ -298,6 +298,65 @@ adc1: adc@5a890000 { status = "disabled"; }; + flexcan1: can@5a8d0000 { + compatible = "fsl,imx8qm-flexcan"; + reg = <0x5a8d0000 0x10000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&can0_lpcg 1>, + <&can0_lpcg 0>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <40000000>; + power-domains = <&pd IMX_SC_R_CAN_0>; + /* SLSlice[4] */ + fsl,clk-source = /bits/ 8 <0>; + fsl,scu-index = /bits/ 8 <0>; + status = "disabled"; + }; + + flexcan2: can@5a8e0000 { + compatible = "fsl,imx8qm-flexcan"; + reg = <0x5a8e0000 0x10000>; + interrupts = ; + interrupt-parent = <&gic>; + /* CAN0 clock and PD is shared among all CAN instances as + * CAN1 shares CAN0's clock and to enable CAN0's clock it + * has to be powered on. + */ + clocks = <&can0_lpcg 1>, + <&can0_lpcg 0>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <40000000>; + power-domains = <&pd IMX_SC_R_CAN_1>; + /* SLSlice[4] */ + fsl,clk-source = /bits/ 8 <0>; + fsl,scu-index = /bits/ 8 <1>; + status = "disabled"; + }; + + flexcan3: can@5a8f0000 { + compatible = "fsl,imx8qm-flexcan"; + reg = <0x5a8f0000 0x10000>; + interrupts = ; + interrupt-parent = <&gic>; + /* CAN0 clock and PD is shared among all CAN instances as + * CAN2 shares CAN0's clock and to enable CAN0's clock it + * has to be powered on. + */ + clocks = <&can0_lpcg 1>, + <&can0_lpcg 0>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <40000000>; + power-domains = <&pd IMX_SC_R_CAN_2>; + /* SLSlice[4] */ + fsl,clk-source = /bits/ 8 <0>; + fsl,scu-index = /bits/ 8 <2>; + status = "disabled"; + }; + i2c0_lpcg: clock-controller@5ac00000 { compatible = "fsl,imx8qxp-lpcg"; reg = <0x5ac00000 0x10000>; @@ -369,4 +428,17 @@ adc1_lpcg: clock-controller@5ac90000 { "adc1_lpcg_ipg_clk"; power-domains = <&pd IMX_SC_R_ADC_1>; }; + + can0_lpcg: clock-controller@5acd0000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5acd0000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>, <&dma_ipg_clk>; + clock-indices = , , ; + clock-output-names = "can0_lpcg_pe_clk", + "can0_lpcg_ipg_clk", + "can0_lpcg_chi_clk"; + power-domains = <&pd IMX_SC_R_CAN_0>; + }; }; -- 2.36.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B6D44C05027 for ; Thu, 26 Jan 2023 11:10:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=9yT5meHR3TaXQtZDJqwMPnQ/CqHDaJ0GKXZ+Bl/Ntg0=; b=r+GhLIg5mPgYaF +KlR9+xtZsNSGMr7XWBTnr0ySmJ+cmxy08BRdG62nGs0WuD+XzahAWTawCRk7XSxYF3uJdfZzrQ3X 991EY9AC4qcHtytTvHh52zu+HXcrhssUbYNPqM+VWHXfZUUqS6d2It4e1YeopUHswHyCptDS9Jn5d 3pmIjq0lxjmSyO2HSyjwyL3K8+3L50ZH8e9x++ulESBrjqd6njpC7Hv6rWrxKT5K6cK/ecJouoLj1 fib60xa2jx/osRA8LE+nH3WDo9PxF7gDXfzomAYVG+7RGtdAykbzqzjcpESErto2RWTlc/qMKu0Xe epRoQ4wm1QAa63t5M5iQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pL08b-00Ae4B-FH; Thu, 26 Jan 2023 11:09:49 +0000 Received: from mout.perfora.net ([74.208.4.194]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1pL087-00AduW-HK for linux-arm-kernel@lists.infradead.org; Thu, 26 Jan 2023 11:09:20 +0000 Received: from toolbox.toradex.int ([31.10.206.125]) by mrelay.perfora.net (mreueus002 [74.208.5.2]) with ESMTPSA (Nemesis) id 0LdHBn-1ov36z12NF-00iR7n; Thu, 26 Jan 2023 12:09:08 +0100 From: Marcel Ziswiler To: devicetree@vger.kernel.org Cc: linux-imx@nxp.com, Liu Ying , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Joakim Zhang , Marcel Ziswiler , Fabio Estevam , Frank Li , Krzysztof Kozlowski , Max Krummenacher , Peng Fan , Pengutronix Kernel Team , Philippe Schenker , Rob Herring , Sascha Hauer , Shawn Guo Subject: [PATCH v5 05/10] arm64: dts: imx8qxp: add flexcan in adma Date: Thu, 26 Jan 2023 12:08:28 +0100 Message-Id: <20230126110833.264439-6-marcel@ziswiler.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20230126110833.264439-1-marcel@ziswiler.com> References: <20230126110833.264439-1-marcel@ziswiler.com> MIME-Version: 1.0 X-Provags-ID: V03:K1:fQWw0GOX+nKPn6Z3NSaSeEwe1U943hr8DyyHXIPa/bsUYvsHEtr +pEppte+ECkpMC1zG1kBn3l6Vxt/Pe5brnOBmN965w9xJpJitFWj2KadZJzPaOrhYKGyTJz 3idB2HSgjvPPXDEWy7uEmcYFvI+Z2Txxyl2ibX4yn40XEve+Lba/uZzZaOtyf5ArQWd3d1P eBti9Pq4N6E5Q3zHTlUdQ== UI-OutboundReport: notjunk:1;M01:P0:ZGgyyNtw80Q=;2HZ8Ryrc35DTl3hfRogXBaLyA6U QgZbQZ0V/4oqkrmBXSPTETFDq13goaWXD7mGcaoFPya8YB/WpYvMAqJZesQCnzcLSEvUgc/a2 VL8YTfaXsPSsEn9a+KkUsV5rAhkvqEw6kuRbzcTsK0dSnfnxdxq4HNunPu6UsNGDfcSnVqVo/ 6HRT7FCDGvltL/7ItWRrQoD+VdXapfyjYzu54bzfbvlYJz5/CmqXNNC2vCFO1qjC+c3m0wg6A jHDaLBu+mU4Rpibh1bE13IfVzhsSF8njc8Naqw1ZUrdYdmclz2pchxzwIgWZcXFzxlfdlFEQ3 KYlAhnCB0UIYBh5+o+kTDYfEDS93+DIbgnF3Xa0QWI+tZiXcWM/YZkR2YtLl9q6iCUhV5VhyQ Hwyz50uGneX7jJZYDE/IChZoiTQsakQlz+HJRqZnc0V1NQpTFk6lBFYdES4iD5sppxnLMrcHW AT2qmRKxdxf3+MImnBAbZfCtdvuAi9mmXcUqpvpUh5FTPBOLq1Qz5kOifVK/ugGVnWtDKlZIh 0Ro4W/mqQmIKgG1M3CCLeVaj3TvX9FC3WLvaJrumhS6+dAloSNXd1Y1y2NReu8APprp0x3uPx mNwuY71LoYTBHpr+EgZJ1QTyfjBdRfZ2IRHEPKhT1yG/80aVSjvlo/Zutz6RjehyO0hyd8QCr M7cvxDEwjvrhxOSlvoFcHh1OKfGYg3C0oWgMpszUow== X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230126_030919_671108_3D934392 X-CRM114-Status: UNSURE ( 9.45 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Joakim Zhang Add FlexCAN decive in adma subsystem. Signed-off-by: Joakim Zhang Signed-off-by: Marcel Ziswiler --- (no changes since v4) Changes in v4: - New patch combining the following downstream patches: commit e8fe3f57223a ("arm64: dts: imx8qxp: add FlexCAN in adma") commit 4e90361f1ed3 ("arm64: dts: imx8qxp: add multi-pd support for CAN1/2") commit 899f516e61f8 ("arm64: dts: imx8: dma: fully switched to new clk binding") commit 8a28ca15a058 ("arm64: dts: imx8qxp: drop multi-pd for CAN device") commit c493402197dd ("arm64: dts: imx8: update CAN fsl,clk-source and fsl,scu-index property") .../arm64/boot/dts/freescale/imx8-ss-dma.dtsi | 72 +++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi index 6ccf926b77a5..2dce8f2ee3ea 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi @@ -298,6 +298,65 @@ adc1: adc@5a890000 { status = "disabled"; }; + flexcan1: can@5a8d0000 { + compatible = "fsl,imx8qm-flexcan"; + reg = <0x5a8d0000 0x10000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&can0_lpcg 1>, + <&can0_lpcg 0>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <40000000>; + power-domains = <&pd IMX_SC_R_CAN_0>; + /* SLSlice[4] */ + fsl,clk-source = /bits/ 8 <0>; + fsl,scu-index = /bits/ 8 <0>; + status = "disabled"; + }; + + flexcan2: can@5a8e0000 { + compatible = "fsl,imx8qm-flexcan"; + reg = <0x5a8e0000 0x10000>; + interrupts = ; + interrupt-parent = <&gic>; + /* CAN0 clock and PD is shared among all CAN instances as + * CAN1 shares CAN0's clock and to enable CAN0's clock it + * has to be powered on. + */ + clocks = <&can0_lpcg 1>, + <&can0_lpcg 0>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <40000000>; + power-domains = <&pd IMX_SC_R_CAN_1>; + /* SLSlice[4] */ + fsl,clk-source = /bits/ 8 <0>; + fsl,scu-index = /bits/ 8 <1>; + status = "disabled"; + }; + + flexcan3: can@5a8f0000 { + compatible = "fsl,imx8qm-flexcan"; + reg = <0x5a8f0000 0x10000>; + interrupts = ; + interrupt-parent = <&gic>; + /* CAN0 clock and PD is shared among all CAN instances as + * CAN2 shares CAN0's clock and to enable CAN0's clock it + * has to be powered on. + */ + clocks = <&can0_lpcg 1>, + <&can0_lpcg 0>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <40000000>; + power-domains = <&pd IMX_SC_R_CAN_2>; + /* SLSlice[4] */ + fsl,clk-source = /bits/ 8 <0>; + fsl,scu-index = /bits/ 8 <2>; + status = "disabled"; + }; + i2c0_lpcg: clock-controller@5ac00000 { compatible = "fsl,imx8qxp-lpcg"; reg = <0x5ac00000 0x10000>; @@ -369,4 +428,17 @@ adc1_lpcg: clock-controller@5ac90000 { "adc1_lpcg_ipg_clk"; power-domains = <&pd IMX_SC_R_ADC_1>; }; + + can0_lpcg: clock-controller@5acd0000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5acd0000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>, <&dma_ipg_clk>; + clock-indices = , , ; + clock-output-names = "can0_lpcg_pe_clk", + "can0_lpcg_ipg_clk", + "can0_lpcg_chi_clk"; + power-domains = <&pd IMX_SC_R_CAN_0>; + }; }; -- 2.36.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel