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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Jan 2023 11:41:49.8349 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bc48fc46-dc52-4a1b-88c6-08db005b7a69 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DBAEUR03FT045.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU0PR08MB9156 We are about to add Realm support where the physical address width may be known via RSI. Make the Physical Address mask dynamic, so that it can be adjusted to the limit for the realm. This will be required for making pages shared, as we introduce the "sharing" attribute as the top bit of the IPA. Signed-off-by: Joey Gouly --- lib/arm/mmu.c | 2 ++ lib/arm/setup.c | 1 + lib/arm64/asm/pgtable-hwdef.h | 6 ------ lib/arm64/asm/pgtable.h | 9 +++++++++ 4 files changed, 12 insertions(+), 6 deletions(-) diff --git a/lib/arm/mmu.c b/lib/arm/mmu.c index e1a72fe4..acaf5614 100644 --- a/lib/arm/mmu.c +++ b/lib/arm/mmu.c @@ -22,6 +22,8 @@ pgd_t *mmu_idmap; +unsigned long phys_mask_shift = 48; + /* CPU 0 starts with disabled MMU */ static cpumask_t mmu_enabled_cpumask; diff --git a/lib/arm/setup.c b/lib/arm/setup.c index bcdf0d78..81052a3d 100644 --- a/lib/arm/setup.c +++ b/lib/arm/setup.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include diff --git a/lib/arm64/asm/pgtable-hwdef.h b/lib/arm64/asm/pgtable-hwdef.h index 8c41fe12..ac95550b 100644 --- a/lib/arm64/asm/pgtable-hwdef.h +++ b/lib/arm64/asm/pgtable-hwdef.h @@ -115,12 +115,6 @@ #define PTE_ATTRINDX(t) (_AT(pteval_t, (t)) << 2) #define PTE_ATTRINDX_MASK (_AT(pteval_t, 7) << 2) -/* - * Highest possible physical address supported. - */ -#define PHYS_MASK_SHIFT (48) -#define PHYS_MASK ((UL(1) << PHYS_MASK_SHIFT) - 1) - /* * TCR flags. */ diff --git a/lib/arm64/asm/pgtable.h b/lib/arm64/asm/pgtable.h index bfb8a993..22ce64f0 100644 --- a/lib/arm64/asm/pgtable.h +++ b/lib/arm64/asm/pgtable.h @@ -21,6 +21,15 @@ #include +extern unsigned long prot_ns_shared; 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Fri, 27 Jan 2023 11:41:33 +0000 From: Joey Gouly To: Andrew Jones , , CC: , Alexandru Elisei , Christoffer Dall , Fuad Tabba , Jean-Philippe Brucker , Joey Gouly , Marc Zyngier , Mark Rutland , Oliver Upton , Paolo Bonzini , Quentin Perret , Steven Price , Suzuki K Poulose , "Thomas Huth" , Will Deacon , Zenghui Yu , , , , Subject: [RFC kvm-unit-tests 04/27] arm: Make physical address mask dynamic Date: Fri, 27 Jan 2023 11:40:45 +0000 Message-ID: <20230127114108.10025-5-joey.gouly@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230127114108.10025-1-joey.gouly@arm.com> References: <20230127112248.136810-1-suzuki.poulose@arm.com> <20230127114108.10025-1-joey.gouly@arm.com> MIME-Version: 1.0 X-EOPAttributedMessage: 1 X-MS-TrafficTypeDiagnostic: AM7EUR03FT040:EE_|PAWPR08MB10240:EE_|DBAEUR03FT010:EE_|DU2PR08MB10085:EE_ X-MS-Office365-Filtering-Correlation-Id: 9d44be54-1a94-4b10-f50d-08db005b7a6b x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; 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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org We are about to add Realm support where the physical address width may be known via RSI. Make the Physical Address mask dynamic, so that it can be adjusted to the limit for the realm. This will be required for making pages shared, as we introduce the "sharing" attribute as the top bit of the IPA. Signed-off-by: Joey Gouly --- lib/arm/mmu.c | 2 ++ lib/arm/setup.c | 1 + lib/arm64/asm/pgtable-hwdef.h | 6 ------ lib/arm64/asm/pgtable.h | 9 +++++++++ 4 files changed, 12 insertions(+), 6 deletions(-) diff --git a/lib/arm/mmu.c b/lib/arm/mmu.c index e1a72fe4..acaf5614 100644 --- a/lib/arm/mmu.c +++ b/lib/arm/mmu.c @@ -22,6 +22,8 @@ pgd_t *mmu_idmap; +unsigned long phys_mask_shift = 48; + /* CPU 0 starts with disabled MMU */ static cpumask_t mmu_enabled_cpumask; diff --git a/lib/arm/setup.c b/lib/arm/setup.c index bcdf0d78..81052a3d 100644 --- a/lib/arm/setup.c +++ b/lib/arm/setup.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include diff --git a/lib/arm64/asm/pgtable-hwdef.h b/lib/arm64/asm/pgtable-hwdef.h index 8c41fe12..ac95550b 100644 --- a/lib/arm64/asm/pgtable-hwdef.h +++ b/lib/arm64/asm/pgtable-hwdef.h @@ -115,12 +115,6 @@ #define PTE_ATTRINDX(t) (_AT(pteval_t, (t)) << 2) #define PTE_ATTRINDX_MASK (_AT(pteval_t, 7) << 2) -/* - * Highest possible physical address supported. - */ -#define PHYS_MASK_SHIFT (48) -#define PHYS_MASK ((UL(1) << PHYS_MASK_SHIFT) - 1) - /* * TCR flags. */ diff --git a/lib/arm64/asm/pgtable.h b/lib/arm64/asm/pgtable.h index bfb8a993..22ce64f0 100644 --- a/lib/arm64/asm/pgtable.h +++ b/lib/arm64/asm/pgtable.h @@ -21,6 +21,15 @@ #include +extern unsigned long prot_ns_shared; +/* + * Highest possible physical address supported. + */ +extern unsigned long phys_mask_shift; +#define PHYS_MASK_SHIFT (phys_mask_shift) +#define PHYS_MASK ((UL(1) << PHYS_MASK_SHIFT) - 1) + + /* * We can convert va <=> pa page table addresses with simple casts * because we always allocate their pages with alloc_page(), and -- 2.17.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel