All of lore.kernel.org
 help / color / mirror / Atom feed
From: Lawrence Hunter <lawrence.hunter@codethink.co.uk>
To: qemu-devel@nongnu.org
Cc: dickon.hood@codethink.co.uk, nazar.kazakov@codethink.co.uk,
	kiran.ostrolenk@codethink.co.uk, frank.chang@sifive.com,
	palmer@dabbelt.com, alistair.francis@wdc.com,
	bin.meng@windriver.com, pbonzini@redhat.com,
	philipp.tomsich@vrull.eu, kvm@vger.kernel.org,
	Lawrence Hunter <lawrence.hunter@codethink.co.uk>
Subject: [PATCH 26/39] target/riscv: Add vsha2c[hl].vv decoding, translation and execution support
Date: Thu,  2 Feb 2023 12:42:17 +0000	[thread overview]
Message-ID: <20230202124230.295997-27-lawrence.hunter@codethink.co.uk> (raw)
In-Reply-To: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk>

Co-authored-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
Signed-off-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk>
---
 target/riscv/helper.h                       |   2 +
 target/riscv/insn32.decode                  |   2 +
 target/riscv/insn_trans/trans_rvzvknh.c.inc |   2 +
 target/riscv/vcrypto_helper.c               | 153 ++++++++++++++++++++
 4 files changed, 159 insertions(+)

diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 6e7777c879..911270c387 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1194,3 +1194,5 @@ DEF_HELPER_5(vaeskf1_vi, void, ptr, ptr, i32, env, i32)
 DEF_HELPER_5(vaeskf2_vi, void, ptr, ptr, i32, env, i32)
 
 DEF_HELPER_5(vsha2ms_vv, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vsha2ch_vv, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vsha2cl_vv, void, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 57fbd63d91..2387bc179c 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -924,3 +924,5 @@ vaeskf2_vi      101010 1 ..... ..... 010 ..... 1110111 @r_vm_1
 
 # *** RV64 Zvknh vector crypto extension ***
 vsha2ms_vv      101101 1 ..... ..... 010 ..... 1110111 @r_vm_1
+vsha2ch_vv      101110 1 ..... ..... 010 ..... 1110111 @r_vm_1
+vsha2cl_vv      101111 1 ..... ..... 010 ..... 1110111 @r_vm_1
diff --git a/target/riscv/insn_trans/trans_rvzvknh.c.inc b/target/riscv/insn_trans/trans_rvzvknh.c.inc
index ff30400100..4d4d26eae5 100644
--- a/target/riscv/insn_trans/trans_rvzvknh.c.inc
+++ b/target/riscv/insn_trans/trans_rvzvknh.c.inc
@@ -43,3 +43,5 @@ static bool vsha_check(DisasContext *s, arg_rmrr *a)
 }
 
 GEN_VV_UNMASKED_TRANS(vsha2ms_vv, vsha_check)
+GEN_VV_UNMASKED_TRANS(vsha2cl_vv, vsha_check)
+GEN_VV_UNMASKED_TRANS(vsha2ch_vv, vsha_check)
diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c
index af596cce09..b73581641a 100644
--- a/target/riscv/vcrypto_helper.c
+++ b/target/riscv/vcrypto_helper.c
@@ -541,3 +541,156 @@ void HELPER(vsha2ms_vv)(void *vd, void *vs1, void *vs2, CPURISCVState *env,
     vext_set_elems_1s(vd, vta, env->vl * esz, total_elems * esz);
     env->vstart = 0;
 }
+
+static inline uint64_t sum0_64(uint64_t x)
+{
+    return ror64(x, 28) ^ ror64(x, 34) ^ ror64(x, 39);
+}
+
+static inline uint32_t sum0_32(uint32_t x)
+{
+    return ror32(x, 2) ^ ror32(x, 13) ^ ror32(x, 22);
+}
+
+static inline uint64_t sum1_64(uint64_t x)
+{
+    return ror64(x, 14) ^ ror64(x, 18) ^ ror64(x, 41);
+}
+
+static inline uint32_t sum1_32(uint32_t x)
+{
+    return ror32(x, 6) ^ ror32(x, 11) ^ ror32(x, 25);
+}
+
+#define ch(x, y, z) ((x & y) ^ ((~x) & z))
+
+#define maj(x, y, z) ((x & y) ^ (x & z) ^ (y & z))
+
+static void vsha2c_64(uint64_t *vs2, uint64_t *vd, uint64_t *vs1)
+{
+    uint64_t a = vs2[3], b = vs2[2], e = vs2[1], f = vs2[0];
+    uint64_t c = vd[3], d = vd[2], g = vd[1], h = vd[0];
+    uint64_t W0 = vs1[0], W1 = vs1[1];
+    uint64_t T1 = h + sum1_64(e) + ch(e, f, g) + W0;
+    uint64_t T2 = sum0_64(a) + maj(a, b, c);
+
+    h = g;
+    g = f;
+    f = e;
+    e = d + T1;
+    d = c;
+    c = b;
+    b = a;
+    a = T1 + T2;
+
+    T1 = h + sum1_64(e) + ch(e, f, g) + W1;
+    T2 = sum0_64(a) + maj(a, b, c);
+    h = g;
+    g = f;
+    f = e;
+    e = d + T1;
+    d = c;
+    c = b;
+    b = a;
+    a = T1 + T2;
+
+    vd[0] = f;
+    vd[1] = e;
+    vd[2] = b;
+    vd[3] = a;
+}
+
+static void vsha2c_32(uint32_t *vs2, uint32_t *vd, uint32_t *vs1)
+{
+    uint32_t a = vs2[H4(3)], b = vs2[H4(2)], e = vs2[H4(1)], f = vs2[H4(0)];
+    uint32_t c = vd[H4(3)], d = vd[H4(2)], g = vd[H4(1)], h = vd[H4(0)];
+    uint32_t W0 = vs1[H4(0)], W1 = vs1[H4(1)];
+    uint32_t T1 = h + sum1_32(e) + ch(e, f, g) + W0;
+    uint32_t T2 = sum0_32(a) + maj(a, b, c);
+
+    h = g;
+    g = f;
+    f = e;
+    e = d + T1;
+    d = c;
+    c = b;
+    b = a;
+    a = T1 + T2;
+
+    T1 = h + sum1_32(e) + ch(e, f, g) + W1;
+    T2 = sum0_32(a) + maj(a, b, c);
+    h = g;
+    g = f;
+    f = e;
+    e = d + T1;
+    d = c;
+    c = b;
+    b = a;
+    a = T1 + T2;
+
+    vd[H4(0)] = f;
+    vd[H4(1)] = e;
+    vd[H4(2)] = b;
+    vd[H4(3)] = a;
+
+}
+
+void HELPER(vsha2ch_vv)(void *vd, void *vs1, void *vs2, CPURISCVState *env,
+                        uint32_t desc)
+{
+    uint32_t sew = FIELD_EX64(env->vtype, VTYPE, VSEW);
+    uint32_t esz = 0;
+    uint32_t total_elems;
+    uint32_t vta = vext_vta(desc);
+
+    if (env->vl % 4 != 0) {
+        riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+    }
+
+    for (uint32_t i = env->vstart / 4; i < env->vl / 4; i++) {
+        if (sew == MO_64) {
+            esz = 8;
+            vsha2c_64(((uint64_t *)vs2) + 4 * i, ((uint64_t *)vd) + 4 * i,
+                        ((uint64_t *)vs1) + 4 * i + 2);
+        } else {
+            esz = 4;
+            vsha2c_32(((uint32_t *)vs2) + 4 * i, ((uint32_t *)vd) + 4 * i,
+                        ((uint32_t *)vs1) + 4 * i + 2);
+        }
+    }
+
+    /* set tail elements to 1s */
+    total_elems = vext_get_total_elems(env, desc, esz);
+    vext_set_elems_1s(vd, vta, env->vl * esz, total_elems * esz);
+    env->vstart = 0;
+}
+
+void HELPER(vsha2cl_vv)(void *vd, void *vs1, void *vs2, CPURISCVState *env,
+                        uint32_t desc)
+{
+    uint32_t sew = FIELD_EX64(env->vtype, VTYPE, VSEW);
+    uint32_t esz = 0;
+    uint32_t total_elems;
+    uint32_t vta = vext_vta(desc);
+
+    if (env->vl % 4 != 0) {
+        riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+    }
+
+    for (uint32_t i = env->vstart / 4; i < env->vl / 4; i++) {
+        if (sew == MO_64) {
+            esz = 8;
+            vsha2c_64(((uint64_t *)vs2) + 4 * i, ((uint64_t *)vd) + 4 * i,
+                        (((uint64_t *)vs1) + 4 * i));
+        } else {
+            esz = 4;
+            vsha2c_32(((uint32_t *)vs2) + 4 * i, ((uint32_t *)vd) + 4 * i,
+                        (((uint32_t *)vs1) + 4 * i));
+        }
+    }
+
+    /* set tail elements to 1s */
+    total_elems = vext_get_total_elems(env, desc, esz);
+    vext_set_elems_1s(vd, vta, env->vl * esz, total_elems * esz);
+    env->vstart = 0;
+}
-- 
2.39.1


  parent reply	other threads:[~2023-02-02 13:19 UTC|newest]

Thread overview: 59+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-02-02 12:41 [PATCH 00/39] Add RISC-V vector cryptography extensions Lawrence Hunter
2023-02-02 12:41 ` [PATCH 01/39] target/riscv: add zvkb cpu property Lawrence Hunter
2023-02-02 12:41 ` [PATCH 02/39] target/riscv: Add vclmul.vv decoding, translation and execution support Lawrence Hunter
2023-02-02 13:53   ` Philipp Tomsich
2023-02-02 12:41 ` [PATCH 03/39] target/riscv: Add vclmul.vx " Lawrence Hunter
2023-02-02 13:59   ` Philipp Tomsich
2023-02-02 12:41 ` [PATCH 04/39] target/riscv: Add vclmulh.vv " Lawrence Hunter
2023-02-02 14:03   ` Philipp Tomsich
2023-02-02 16:54   ` Richard Henderson
2023-02-02 12:41 ` [PATCH 05/39] target/riscv: Add vclmulh.vx " Lawrence Hunter
2023-02-02 12:41 ` [PATCH 06/39] target/riscv: Add vrol.[vv,vx] and vror.[vv,vx,vi] " Lawrence Hunter
2023-02-02 12:41   ` [PATCH 06/39] target/riscv: Add vrol.[vv, vx] and vror.[vv, vx, vi] " Lawrence Hunter
2023-02-02 14:13   ` [PATCH 06/39] target/riscv: Add vrol.[vv,vx] and vror.[vv,vx,vi] " Philipp Tomsich
2023-02-02 14:13     ` [PATCH 06/39] target/riscv: Add vrol.[vv, vx] and vror.[vv, vx, vi] " Philipp Tomsich
2023-02-02 14:30     ` [PATCH 06/39] target/riscv: Add vrol.[vv,vx] and vror.[vv,vx,vi] " Philipp Tomsich
2023-02-02 14:30       ` [PATCH 06/39] target/riscv: Add vrol.[vv, vx] and vror.[vv, vx, vi] " Philipp Tomsich
2023-02-02 17:35       ` Richard Henderson
2023-02-02 18:07         ` Philipp Tomsich
2023-02-02 23:14           ` Richard Henderson
2023-02-02 12:41 ` [PATCH 07/39] target/riscv: Add vbrev8.v " Lawrence Hunter
2023-02-02 14:21   ` Philipp Tomsich
2023-02-02 12:41 ` [PATCH 08/39] target/riscv: Add vrev8.v " Lawrence Hunter
2023-02-02 14:22   ` Philipp Tomsich
2023-02-02 12:42 ` [PATCH 09/39] target/riscv: Add vandn.[vv,vx,vi] " Lawrence Hunter
2023-02-02 12:42   ` [PATCH 09/39] target/riscv: Add vandn.[vv, vx, vi] " Lawrence Hunter
2023-02-02 14:29   ` [PATCH 09/39] target/riscv: Add vandn.[vv,vx,vi] " Philipp Tomsich
2023-02-02 12:42 ` [PATCH 10/39] target/riscv: expose zvkb cpu property Lawrence Hunter
2023-02-02 14:23   ` Philipp Tomsich
2023-02-02 14:24     ` Philipp Tomsich
2023-02-02 12:42 ` [PATCH 11/39] target/riscv: add zvkns " Lawrence Hunter
2023-02-02 12:42 ` [PATCH 12/39] target/riscv: Add vaesef.vv decoding, translation and execution support Lawrence Hunter
2023-02-02 12:42 ` [PATCH 13/39] target/riscv: Add vaesef.vs " Lawrence Hunter
2023-02-02 12:42 ` [PATCH 14/39] target/riscv: Add vaesdf.vv " Lawrence Hunter
2023-02-02 12:42 ` [PATCH 15/39] target/riscv: Add vaesdf.vs " Lawrence Hunter
2023-02-02 12:42 ` [PATCH 16/39] target/riscv: Add vaesdm.vv " Lawrence Hunter
2023-02-02 12:42 ` [PATCH 17/39] target/riscv: Add vaesdm.vs " Lawrence Hunter
2023-02-02 12:42 ` [PATCH 18/39] target/riscv: Add vaesz.vs " Lawrence Hunter
2023-02-02 12:42 ` [PATCH 19/39] target/riscv: Add vaesem.vv " Lawrence Hunter
2023-02-02 12:42 ` [PATCH 20/39] target/riscv: Add vaesem.vs " Lawrence Hunter
2023-02-02 12:42 ` [PATCH 21/39] target/riscv: Add vaeskf1.vi " Lawrence Hunter
2023-02-02 12:42 ` [PATCH 22/39] target/riscv: Add vaeskf2.vi " Lawrence Hunter
2023-02-02 12:42 ` [PATCH 23/39] target/riscv: expose zvkns cpu property Lawrence Hunter
2023-02-02 12:42 ` [PATCH 24/39] target/riscv: add zvknh cpu properties Lawrence Hunter
2023-02-02 12:42 ` [PATCH 25/39] target/riscv: Add vsha2ms.vv decoding, translation and execution support Lawrence Hunter
2023-02-02 12:42 ` Lawrence Hunter [this message]
2023-02-02 12:42 ` [PATCH 27/39] target/riscv: expose zvknh cpu properties Lawrence Hunter
2023-02-02 12:42 ` [PATCH 28/39] target/riscv: add zvksh cpu property Lawrence Hunter
2023-02-02 12:42 ` [PATCH 29/39] target/riscv: Add vsm3me.vv decoding, translation and execution support Lawrence Hunter
2023-02-02 12:42 ` [PATCH 30/39] target/riscv: Add vsm3c.vi " Lawrence Hunter
2023-02-02 12:42 ` [PATCH 31/39] target/riscv: expose zvksh cpu property Lawrence Hunter
2023-02-02 12:42 ` [PATCH 32/39] target/riscv: add zvkg " Lawrence Hunter
2023-02-02 12:42 ` [PATCH 33/39] target/riscv: Add vghmac.vv decoding, translation and execution support Lawrence Hunter
2023-02-02 12:42 ` [PATCH 34/39] target/riscv: expose zvkg cpu property Lawrence Hunter
2023-02-02 12:42 ` [PATCH 35/39] crypto: Move SM4_SBOXWORD from target/riscv Lawrence Hunter
2023-02-02 17:02   ` Richard Henderson
2023-02-02 12:42 ` [PATCH 36/39] crypto: Add SM4 constant parameter CK Lawrence Hunter
2023-02-02 12:42 ` [PATCH 37/39] target/riscv: Add zvksed cfg property Lawrence Hunter
2023-02-02 12:42 ` [PATCH 38/39] target/riscv: Add Zvksed support Lawrence Hunter
2023-02-02 12:42 ` [PATCH 39/39] target/riscv: Expose Zvksed property Lawrence Hunter

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20230202124230.295997-27-lawrence.hunter@codethink.co.uk \
    --to=lawrence.hunter@codethink.co.uk \
    --cc=alistair.francis@wdc.com \
    --cc=bin.meng@windriver.com \
    --cc=dickon.hood@codethink.co.uk \
    --cc=frank.chang@sifive.com \
    --cc=kiran.ostrolenk@codethink.co.uk \
    --cc=kvm@vger.kernel.org \
    --cc=nazar.kazakov@codethink.co.uk \
    --cc=palmer@dabbelt.com \
    --cc=pbonzini@redhat.com \
    --cc=philipp.tomsich@vrull.eu \
    --cc=qemu-devel@nongnu.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.