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([177.102.69.207]) by smtp.gmail.com with ESMTPSA id m24-20020a05680806d800b00377fae9d36csm6707382oih.52.2023.02.02.05.58.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Feb 2023 05:58:14 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza Subject: [PATCH v10 0/3] hw/riscv: handle kernel_entry high bits with 32bit CPUs Date: Thu, 2 Feb 2023 10:58:07 -0300 Message-Id: <20230202135810.1657792-1-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::241; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x241.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi, This new version removed the translate_fn() from patch 1 because it wasn't removing the sign-extension for pentry as we thought it would. A more detailed explanation is given in the commit msg of patch 1. We're now retrieving the 'lowaddr' value from load_elf_ram_sym() and using it when we're running a 32-bit CPU. This worked with 32 bit 'virt' machine booting with the -kernel option. If this approach doesn't work for the Xvisor use case, IMO we should just filter kernel_load_addr bits directly as we were doing a handful of versions ago. Patches are based on current riscv-to-apply.next. Changes from v9: - patch 1: - removed the translate_fn() callback - return 'kernel_low' when running a 32-bit CPU - v9 link: https://lists.gnu.org/archive/html/qemu-devel/2023-01/msg04509.html Daniel Henrique Barboza (3): hw/riscv: handle 32 bit CPUs kernel_addr in riscv_load_kernel() hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel() hw/riscv/boot.c: make riscv_load_initrd() static hw/riscv/boot.c | 96 +++++++++++++++++++++++--------------- hw/riscv/microchip_pfsoc.c | 12 +---- hw/riscv/opentitan.c | 4 +- hw/riscv/sifive_e.c | 4 +- hw/riscv/sifive_u.c | 12 +---- hw/riscv/spike.c | 14 ++---- hw/riscv/virt.c | 12 +---- include/hw/riscv/boot.h | 3 +- 8 files changed, 76 insertions(+), 81 deletions(-) -- 2.39.1