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charset=UTF-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=216.71.153.141; envelope-from=prvs=395dd5341=alistair.francis@opensource.wdc.com; helo=esa3.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Christoph M=C3=BCllner This patch adds support for the T-Head MAC instructions. The patch uses the T-Head specific decoder and translation. Co-developed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Christoph M=C3=BCllner Message-Id: <20230131202013.2541053-8-christoph.muellner@vrull.eu> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 1 + target/riscv/xthead.decode | 8 +++ target/riscv/cpu.c | 2 + target/riscv/translate.c | 3 +- target/riscv/insn_trans/trans_xthead.c.inc | 83 ++++++++++++++++++++++ 5 files changed, 96 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index a313e025e7..830b20558c 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -478,6 +478,7 @@ struct RISCVCPUConfig { bool ext_xtheadbs; bool ext_xtheadcmo; bool ext_xtheadcondmov; + bool ext_xtheadmac; bool ext_xtheadsync; bool ext_XVentanaCondOps; =20 diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode index a8ebd8a18b..696de6cecf 100644 --- a/target/riscv/xthead.decode +++ b/target/riscv/xthead.decode @@ -88,6 +88,14 @@ th_l2cache_iall 0000000 10110 00000 000 00000 0001011 th_mveqz 0100000 ..... ..... 001 ..... 0001011 @r th_mvnez 0100001 ..... ..... 001 ..... 0001011 @r =20 +# XTheadMac +th_mula 00100 00 ..... ..... 001 ..... 0001011 @r +th_mulah 00101 00 ..... ..... 001 ..... 0001011 @r +th_mulaw 00100 10 ..... ..... 001 ..... 0001011 @r +th_muls 00100 01 ..... ..... 001 ..... 0001011 @r +th_mulsh 00101 01 ..... ..... 001 ..... 0001011 @r +th_mulsw 00100 11 ..... ..... 001 ..... 0001011 @r + # XTheadSync th_sfence_vmas 0000010 ..... ..... 000 00000 0001011 @rs2_s th_sync 0000000 11000 00000 000 00000 0001011 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 13b065bc68..88da4de14d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -114,6 +114,7 @@ static const struct isa_ext_data isa_edata_arr[] =3D = { ISA_EXT_DATA_ENTRY(xtheadbs, true, PRIV_VERSION_1_11_0, ext_xtheadbs= ), ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadc= mo), ISA_EXT_DATA_ENTRY(xtheadcondmov, true, PRIV_VERSION_1_11_0, ext_xth= eadcondmov), + ISA_EXT_DATA_ENTRY(xtheadmac, true, PRIV_VERSION_1_11_0, ext_xtheadm= ac), ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, ext_xthead= sync), ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_X= VentanaCondOps), }; @@ -1099,6 +1100,7 @@ static Property riscv_cpu_extensions[] =3D { DEFINE_PROP_BOOL("xtheadbs", RISCVCPU, cfg.ext_xtheadbs, false), DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, f= alse), + DEFINE_PROP_BOOL("xtheadmac", RISCVCPU, cfg.ext_xtheadmac, false), DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false), DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOp= s, false), =20 diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 4f4c09cd68..e5a57a8516 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -134,7 +134,8 @@ static bool has_xthead_p(DisasContext *ctx __attribu= te__((__unused__))) { return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb || ctx->cfg_ptr->ext_xtheadbs || ctx->cfg_ptr->ext_xtheadcmo || - ctx->cfg_ptr->ext_xtheadcondmov || ctx->cfg_ptr->ext_xtheadsy= nc; + ctx->cfg_ptr->ext_xtheadcondmov || ctx->cfg_ptr->ext_xtheadma= c || + ctx->cfg_ptr->ext_xtheadsync; } =20 #define MATERIALISE_EXT_PREDICATE(ext) \ diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/in= sn_trans/trans_xthead.c.inc index 089b51f468..31a4034927 100644 --- a/target/riscv/insn_trans/trans_xthead.c.inc +++ b/target/riscv/insn_trans/trans_xthead.c.inc @@ -46,6 +46,12 @@ } \ } while (0) =20 +#define REQUIRE_XTHEADMAC(ctx) do { \ + if (!ctx->cfg_ptr->ext_xtheadmac) { \ + return false; \ + } \ +} while (0) + #define REQUIRE_XTHEADSYNC(ctx) do { \ if (!ctx->cfg_ptr->ext_xtheadsync) { \ return false; \ @@ -299,6 +305,83 @@ static bool trans_th_mvnez(DisasContext *ctx, arg_th= _mveqz *a) return gen_th_condmove(ctx, a, TCG_COND_NE); } =20 +/* XTheadMac */ + +static bool gen_th_mac(DisasContext *ctx, arg_r *a, + void (*accumulate_func)(TCGv, TCGv, TCGv), + void (*extend_operand_func)(TCGv, TCGv)) +{ + TCGv dest =3D dest_gpr(ctx, a->rd); + TCGv src0 =3D get_gpr(ctx, a->rd, EXT_NONE); + TCGv src1 =3D get_gpr(ctx, a->rs1, EXT_NONE); + TCGv src2 =3D get_gpr(ctx, a->rs2, EXT_NONE); + TCGv tmp =3D tcg_temp_new(); + + if (extend_operand_func) { + TCGv tmp2 =3D tcg_temp_new(); + extend_operand_func(tmp, src1); + extend_operand_func(tmp2, src2); + tcg_gen_mul_tl(tmp, tmp, tmp2); + tcg_temp_free(tmp2); + } else { + tcg_gen_mul_tl(tmp, src1, src2); + } + + accumulate_func(dest, src0, tmp); + gen_set_gpr(ctx, a->rd, dest); + tcg_temp_free(tmp); + + return true; +} + +/* th.mula: "rd =3D rd + rs1 * rs2" */ +static bool trans_th_mula(DisasContext *ctx, arg_th_mula *a) +{ + REQUIRE_XTHEADMAC(ctx); + return gen_th_mac(ctx, a, tcg_gen_add_tl, NULL); +} + +/* th.mulah: "rd =3D sext.w(rd + sext.w(rs1[15:0]) * sext.w(rs2[15:0]))"= */ +static bool trans_th_mulah(DisasContext *ctx, arg_th_mulah *a) +{ + REQUIRE_XTHEADMAC(ctx); + ctx->ol =3D MXL_RV32; + return gen_th_mac(ctx, a, tcg_gen_add_tl, tcg_gen_ext16s_tl); +} + +/* th.mulaw: "rd =3D sext.w(rd + rs1 * rs2)" */ +static bool trans_th_mulaw(DisasContext *ctx, arg_th_mulaw *a) +{ + REQUIRE_XTHEADMAC(ctx); + REQUIRE_64BIT(ctx); + ctx->ol =3D MXL_RV32; + return gen_th_mac(ctx, a, tcg_gen_add_tl, NULL); +} + +/* th.muls: "rd =3D rd - rs1 * rs2" */ +static bool trans_th_muls(DisasContext *ctx, arg_th_muls *a) +{ + REQUIRE_XTHEADMAC(ctx); + return gen_th_mac(ctx, a, tcg_gen_sub_tl, NULL); +} + +/* th.mulsh: "rd =3D sext.w(rd - sext.w(rs1[15:0]) * sext.w(rs2[15:0]))"= */ +static bool trans_th_mulsh(DisasContext *ctx, arg_th_mulsh *a) +{ + REQUIRE_XTHEADMAC(ctx); + ctx->ol =3D MXL_RV32; + return gen_th_mac(ctx, a, tcg_gen_sub_tl, tcg_gen_ext16s_tl); +} + +/* th.mulsw: "rd =3D sext.w(rd - rs1 * rs2)" */ +static bool trans_th_mulsw(DisasContext *ctx, arg_th_mulsw *a) +{ + REQUIRE_XTHEADMAC(ctx); + REQUIRE_64BIT(ctx); + ctx->ol =3D MXL_RV32; + return gen_th_mac(ctx, a, tcg_gen_sub_tl, NULL); +} + /* XTheadSync */ =20 static bool trans_th_sfence_vmas(DisasContext *ctx, arg_th_sfence_vmas *= a) --=20 2.39.1