From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com,
"Christoph Müllner" <christoph.muellner@vrull.eu>,
"LIU Zhiwei" <zhiwei_liu@linux.alibaba.com>,
"Alistair Francis" <alistair.francis@wdc.com>,
"Richard Henderson" <richard.henderson@linaro.org>
Subject: [PULL 22/32] RISC-V: Adding T-Head MemPair extension
Date: Tue, 7 Feb 2023 17:09:33 +1000 [thread overview]
Message-ID: <20230207070943.2558857-23-alistair.francis@opensource.wdc.com> (raw)
In-Reply-To: <20230207070943.2558857-1-alistair.francis@opensource.wdc.com>
From: Christoph Müllner <christoph.muellner@vrull.eu>
This patch adds support for the T-Head MemPair instructions.
The patch uses the T-Head specific decoder and translation.
Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Message-Id: <20230131202013.2541053-9-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 1 +
target/riscv/xthead.decode | 13 +++
target/riscv/cpu.c | 2 +
target/riscv/translate.c | 2 +-
target/riscv/insn_trans/trans_xthead.c.inc | 92 ++++++++++++++++++++++
5 files changed, 109 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 830b20558c..38e80d44d5 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -479,6 +479,7 @@ struct RISCVCPUConfig {
bool ext_xtheadcmo;
bool ext_xtheadcondmov;
bool ext_xtheadmac;
+ bool ext_xtheadmempair;
bool ext_xtheadsync;
bool ext_XVentanaCondOps;
diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode
index 696de6cecf..ff2a83b56d 100644
--- a/target/riscv/xthead.decode
+++ b/target/riscv/xthead.decode
@@ -11,16 +11,21 @@
# Fields:
%rd 7:5
+%rd1 7:5
+%rs 15:5
%rs1 15:5
+%rd2 20:5
%rs2 20:5
%sh5 20:5
%sh6 20:6
+%sh2 25:2
# Argument sets
&r rd rs1 rs2 !extern
&r2 rd rs1 !extern
&shift shamt rs1 rd !extern
&th_bfext msb lsb rs1 rd
+&th_pair rd1 rs rd2 sh2
# Formats
@sfence_vm ....... ..... ..... ... ..... ....... %rs1
@@ -30,6 +35,7 @@
@th_bfext msb:6 lsb:6 ..... ... ..... ....... &th_bfext %rs1 %rd
@sh5 ....... ..... ..... ... ..... ....... &shift shamt=%sh5 %rs1 %rd
@sh6 ...... ...... ..... ... ..... ....... &shift shamt=%sh6 %rs1 %rd
+@th_pair ..... .. ..... ..... ... ..... ....... &th_pair %rd1 %rs %rd2 %sh2
# XTheadBa
# Instead of defining a new encoding, we simply use the decoder to
@@ -96,6 +102,13 @@ th_muls 00100 01 ..... ..... 001 ..... 0001011 @r
th_mulsh 00101 01 ..... ..... 001 ..... 0001011 @r
th_mulsw 00100 11 ..... ..... 001 ..... 0001011 @r
+# XTheadMemPair
+th_ldd 11111 .. ..... ..... 100 ..... 0001011 @th_pair
+th_lwd 11100 .. ..... ..... 100 ..... 0001011 @th_pair
+th_lwud 11110 .. ..... ..... 100 ..... 0001011 @th_pair
+th_sdd 11111 .. ..... ..... 101 ..... 0001011 @th_pair
+th_swd 11100 .. ..... ..... 101 ..... 0001011 @th_pair
+
# XTheadSync
th_sfence_vmas 0000010 ..... ..... 000 00000 0001011 @rs2_s
th_sync 0000000 11000 00000 000 00000 0001011
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 88da4de14d..b7047d139d 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -115,6 +115,7 @@ static const struct isa_ext_data isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo),
ISA_EXT_DATA_ENTRY(xtheadcondmov, true, PRIV_VERSION_1_11_0, ext_xtheadcondmov),
ISA_EXT_DATA_ENTRY(xtheadmac, true, PRIV_VERSION_1_11_0, ext_xtheadmac),
+ ISA_EXT_DATA_ENTRY(xtheadmempair, true, PRIV_VERSION_1_11_0, ext_xtheadmempair),
ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, ext_xtheadsync),
ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVentanaCondOps),
};
@@ -1101,6 +1102,7 @@ static Property riscv_cpu_extensions[] = {
DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false),
DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, false),
DEFINE_PROP_BOOL("xtheadmac", RISCVCPU, cfg.ext_xtheadmac, false),
+ DEFINE_PROP_BOOL("xtheadmempair", RISCVCPU, cfg.ext_xtheadmempair, false),
DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false),
DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false),
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index e5a57a8516..f383e69db3 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -135,7 +135,7 @@ static bool has_xthead_p(DisasContext *ctx __attribute__((__unused__)))
return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb ||
ctx->cfg_ptr->ext_xtheadbs || ctx->cfg_ptr->ext_xtheadcmo ||
ctx->cfg_ptr->ext_xtheadcondmov || ctx->cfg_ptr->ext_xtheadmac ||
- ctx->cfg_ptr->ext_xtheadsync;
+ ctx->cfg_ptr->ext_xtheadmempair || ctx->cfg_ptr->ext_xtheadsync;
}
#define MATERIALISE_EXT_PREDICATE(ext) \
diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn_trans/trans_xthead.c.inc
index 31a4034927..f1bd0dbad5 100644
--- a/target/riscv/insn_trans/trans_xthead.c.inc
+++ b/target/riscv/insn_trans/trans_xthead.c.inc
@@ -52,6 +52,12 @@
} \
} while (0)
+#define REQUIRE_XTHEADMEMPAIR(ctx) do { \
+ if (!ctx->cfg_ptr->ext_xtheadmempair) { \
+ return false; \
+ } \
+} while (0)
+
#define REQUIRE_XTHEADSYNC(ctx) do { \
if (!ctx->cfg_ptr->ext_xtheadsync) { \
return false; \
@@ -382,6 +388,92 @@ static bool trans_th_mulsw(DisasContext *ctx, arg_th_mulsw *a)
return gen_th_mac(ctx, a, tcg_gen_sub_tl, NULL);
}
+/* XTheadMemPair */
+
+static bool gen_loadpair_tl(DisasContext *ctx, arg_th_pair *a, MemOp memop,
+ int shamt)
+{
+ if (a->rs == a->rd1 || a->rs == a->rd2 || a->rd1 == a->rd2) {
+ return false;
+ }
+
+ TCGv t1 = tcg_temp_new();
+ TCGv t2 = tcg_temp_new();
+ TCGv addr1 = tcg_temp_new();
+ TCGv addr2 = tcg_temp_new();
+ int imm = a->sh2 << shamt;
+
+ addr1 = get_address(ctx, a->rs, imm);
+ addr2 = get_address(ctx, a->rs, memop_size(memop) + imm);
+
+ tcg_gen_qemu_ld_tl(t1, addr1, ctx->mem_idx, memop);
+ tcg_gen_qemu_ld_tl(t2, addr2, ctx->mem_idx, memop);
+ gen_set_gpr(ctx, a->rd1, t1);
+ gen_set_gpr(ctx, a->rd2, t2);
+
+ tcg_temp_free(t1);
+ tcg_temp_free(t2);
+ tcg_temp_free(addr1);
+ tcg_temp_free(addr2);
+ return true;
+}
+
+static bool trans_th_ldd(DisasContext *ctx, arg_th_pair *a)
+{
+ REQUIRE_XTHEADMEMPAIR(ctx);
+ REQUIRE_64BIT(ctx);
+ return gen_loadpair_tl(ctx, a, MO_TESQ, 4);
+}
+
+static bool trans_th_lwd(DisasContext *ctx, arg_th_pair *a)
+{
+ REQUIRE_XTHEADMEMPAIR(ctx);
+ return gen_loadpair_tl(ctx, a, MO_TESL, 3);
+}
+
+static bool trans_th_lwud(DisasContext *ctx, arg_th_pair *a)
+{
+ REQUIRE_XTHEADMEMPAIR(ctx);
+ return gen_loadpair_tl(ctx, a, MO_TEUL, 3);
+}
+
+static bool gen_storepair_tl(DisasContext *ctx, arg_th_pair *a, MemOp memop,
+ int shamt)
+{
+ if (a->rs == a->rd1 || a->rs == a->rd2 || a->rd1 == a->rd2) {
+ return false;
+ }
+
+ TCGv data1 = get_gpr(ctx, a->rd1, EXT_NONE);
+ TCGv data2 = get_gpr(ctx, a->rd2, EXT_NONE);
+ TCGv addr1 = tcg_temp_new();
+ TCGv addr2 = tcg_temp_new();
+ int imm = a->sh2 << shamt;
+
+ addr1 = get_address(ctx, a->rs, imm);
+ addr2 = get_address(ctx, a->rs, memop_size(memop) + imm);
+
+ tcg_gen_qemu_st_tl(data1, addr1, ctx->mem_idx, memop);
+ tcg_gen_qemu_st_tl(data2, addr2, ctx->mem_idx, memop);
+
+ tcg_temp_free(addr1);
+ tcg_temp_free(addr2);
+ return true;
+}
+
+static bool trans_th_sdd(DisasContext *ctx, arg_th_pair *a)
+{
+ REQUIRE_XTHEADMEMPAIR(ctx);
+ REQUIRE_64BIT(ctx);
+ return gen_storepair_tl(ctx, a, MO_TESQ, 4);
+}
+
+static bool trans_th_swd(DisasContext *ctx, arg_th_pair *a)
+{
+ REQUIRE_XTHEADMEMPAIR(ctx);
+ return gen_storepair_tl(ctx, a, MO_TESL, 3);
+}
+
/* XTheadSync */
static bool trans_th_sfence_vmas(DisasContext *ctx, arg_th_sfence_vmas *a)
--
2.39.1
next prev parent reply other threads:[~2023-02-07 7:18 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-07 7:09 [PULL 00/32] riscv-to-apply queue Alistair Francis
2023-02-07 7:09 ` [PULL 01/32] target/riscv: update disas.c for xnor/orn/andn and slli.uw Alistair Francis
2023-02-07 7:09 ` [PULL 02/32] include/hw/riscv/opentitan: update opentitan IRQs Alistair Francis
2023-02-07 7:09 ` [PULL 03/32] hw/riscv: boot: Don't use CSRs if they are disabled Alistair Francis
2023-02-07 7:09 ` [PULL 04/32] target/riscv: Update VS timer whenever htimedelta changes Alistair Francis
2023-02-07 7:09 ` [PULL 05/32] target/riscv: Don't clear mask in riscv_cpu_update_mip() for VSTIP Alistair Francis
2023-02-07 7:09 ` [PULL 06/32] target/riscv: No need to re-start QEMU timer when timecmp == UINT64_MAX Alistair Francis
2023-02-07 7:09 ` [PULL 07/32] target/riscv: Ensure opcode is saved for all relevant instructions Alistair Francis
2023-02-07 7:09 ` [PULL 08/32] hw/riscv/virt.c: calculate socket count once in create_fdt_imsic() Alistair Francis
2023-02-07 7:09 ` [PULL 09/32] hw/riscv/virt.c: rename MachineState 'mc' pointers to 'ms' Alistair Francis
2023-02-07 7:09 ` [PULL 10/32] hw/riscv/spike.c: rename MachineState 'mc' pointers to' ms' Alistair Francis
2023-02-07 7:09 ` [PULL 11/32] target/riscv: set tval for triggered watchpoints Alistair Francis
2023-02-07 7:09 ` [PULL 12/32] hw/riscv/boot.c: calculate fdt size after fdt_pack() Alistair Francis
2023-02-07 7:09 ` [PULL 13/32] hw/riscv: split fdt address calculation from fdt load Alistair Francis
2023-02-07 7:09 ` [PULL 14/32] hw/riscv: change riscv_compute_fdt_addr() semantics Alistair Francis
2023-02-07 7:09 ` [PULL 15/32] RISC-V: Adding XTheadCmo ISA extension Alistair Francis
2023-02-07 7:09 ` [PULL 16/32] RISC-V: Adding XTheadSync " Alistair Francis
2023-02-07 7:09 ` [PULL 17/32] RISC-V: Adding XTheadBa " Alistair Francis
2023-02-07 7:09 ` [PULL 18/32] RISC-V: Adding XTheadBb " Alistair Francis
2023-02-07 7:09 ` [PULL 19/32] RISC-V: Adding XTheadBs " Alistair Francis
2023-02-07 7:09 ` [PULL 20/32] RISC-V: Adding XTheadCondMov " Alistair Francis
2023-02-07 7:09 ` [PULL 21/32] RISC-V: Adding T-Head multiply-accumulate instructions Alistair Francis
2023-02-07 7:09 ` Alistair Francis [this message]
2023-02-07 7:09 ` [PULL 23/32] RISC-V: Adding T-Head MemIdx extension Alistair Francis
2023-02-07 7:09 ` [PULL 24/32] RISC-V: Adding T-Head FMemIdx extension Alistair Francis
2023-02-07 7:09 ` [PULL 25/32] RISC-V: Set minimum priv version for Zfh to 1.11 Alistair Francis
2023-02-07 7:09 ` [PULL 26/32] RISC-V: Add initial support for T-Head C906 Alistair Francis
2023-02-07 7:09 ` [PULL 27/32] RISC-V: Adding XTheadFmv ISA extension Alistair Francis
2023-02-07 7:09 ` [PULL 28/32] target/riscv: add a MAINTAINERS entry for XThead* extension support Alistair Francis
2023-02-07 7:09 ` [PULL 29/32] target/riscv: fix for virtual instr exception Alistair Francis
2023-02-07 7:09 ` [PULL 30/32] target/riscv: fix ctzw behavior Alistair Francis
2023-02-07 7:09 ` [PULL 31/32] target/riscv: fix SBI getchar handler for KVM Alistair Francis
2023-02-07 7:09 ` [PULL 32/32] hw/riscv: virt: Simplify virt_{get,set}_aclint() Alistair Francis
2023-02-07 20:12 ` [PULL 00/32] riscv-to-apply queue Peter Maydell
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