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From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
To: joro@8bytes.org, will@kernel.org, robin.murphy@arm.com,
	robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org
Cc: iommu@lists.linux.dev, devicetree@vger.kernel.org,
	linux-renesas-soc@vger.kernel.org,
	Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Subject: [PATCH v3] dt-bindings: iommu: renesas,ipmmu-vmsa: Update for R-Car Gen4
Date: Thu,  9 Feb 2023 22:34:40 +0900	[thread overview]
Message-ID: <20230209133440.2643228-1-yoshihiro.shimoda.uh@renesas.com> (raw)

Since R-Car Gen4 doens't have the main IPMMU IMSSTR register, update
the renesas,ipmmu-main property which sets maxItems as 1.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
Changes from v2:
https://lore.kernel.org/all/20230127140446.1728102-1-yoshihiro.shimoda.uh@renesas.com/
 - Set maxItems to renesas,ipmmu-main if R-Car Gen4.

Changes from v1:
https://lore.kernel.org/all/20230123012940.1250879-1-yoshihiro.shimoda.uh@renesas.com/
 - Change number of argument for R-Car Gen4 instead of "module id".
   On the discussion, using 'minItems' is a solution. But, it causes
   "too short" errors on dtbs_check. So, using "oneOf" instead.

 .../bindings/iommu/renesas,ipmmu-vmsa.yaml    | 19 ++++++++++++++-----
 1 file changed, 14 insertions(+), 5 deletions(-)

diff --git a/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.yaml b/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.yaml
index 72308a4c14e7..cc81bce44f3f 100644
--- a/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.yaml
+++ b/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.yaml
@@ -74,11 +74,10 @@ properties:
   renesas,ipmmu-main:
     $ref: /schemas/types.yaml#/definitions/phandle-array
     items:
-      - items:
-          - description: phandle to main IPMMU
-          - description: the interrupt bit number associated with the particular
-              cache IPMMU device. The interrupt bit number needs to match the main
-              IPMMU IMSSTR register. Only used by cache IPMMU instances.
+      - description: phandle to main IPMMU
+      - description: the interrupt bit number associated with the particular
+          cache IPMMU device. The interrupt bit number needs to match the main
+          IPMMU IMSSTR register. Only used by cache IPMMU instances.
     description:
       Reference to the main IPMMU phandle plus 1 cell. The cell is
       the interrupt bit number associated with the particular cache IPMMU
@@ -109,6 +108,16 @@ allOf:
       required:
         - power-domains
 
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: renesas,rcar-gen4-ipmmu-vmsa
+    then:
+      properties:
+        renesas,ipmmu-main:
+          maxItems: 1
+
 examples:
   - |
     #include <dt-bindings/clock/r8a7791-cpg-mssr.h>
-- 
2.25.1


             reply	other threads:[~2023-02-09 13:35 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-02-09 13:34 Yoshihiro Shimoda [this message]
2023-02-09 14:46 ` [PATCH v3] dt-bindings: iommu: renesas,ipmmu-vmsa: Update for R-Car Gen4 Rob Herring
2023-02-09 17:01   ` Geert Uytterhoeven
2023-02-09 14:58 ` Rob Herring

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