From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4376AC6FD19 for ; Tue, 14 Mar 2023 00:41:06 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 31E0D8615A; Tue, 14 Mar 2023 01:39:48 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=reject dis=none) header.from=kwiboo.se Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=kwiboo.se header.i=@kwiboo.se header.b="G5QtNVE8"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 4B6D685DBB; Tue, 14 Mar 2023 01:38:45 +0100 (CET) Received: from wrqvtbkv.outbound-mail.sendgrid.net (wrqvtbkv.outbound-mail.sendgrid.net [149.72.123.24]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 1860E85D7B for ; Tue, 14 Mar 2023 01:38:33 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=reject dis=none) header.from=kwiboo.se Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=bounces+31435339-7456-u-boot=lists.denx.de@em2124.kwiboo.se DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kwiboo.se; h=from:subject:in-reply-to:references:mime-version:to:cc: content-transfer-encoding:content-type:cc:content-type:from:subject:to; s=s1; bh=bUJjUQKNyrx+fJipiCChqR66iCeeJbrz9r/iw1l784g=; b=G5QtNVE8ReUU+dH1hr3xgdHohb04p0TS1mnxl0fE0JAk6NeNXIyVE+opsdPSFh08GRRS YM734OK2IHiZLiUhwwy54EcXgHrKI0KscT4uJ8Xu249L4vOFXON4fyVktexUVm2ruxxNPS a2YyLkbYxZ6pw3m/HOxkgiYx8Lw06mWhBUTCzDeDKkU6Hb/FSu6mx/3lwUQRc/5MB7X3I2 p86xed2RCV+nkn4JCufeBN6nqBda+z8TzeyotArY7ZfHW7Ev3sDDloGSE/ZmuFl0IPdlz1 PPZWZjNSHIOXC2peHxMzIfFpxyGCrFby2ygk65iJ8Kogqd1QGgyv01i2ZTHNGz9g== Received: by filterdrecv-68f8d557c9-z8zks with SMTP id filterdrecv-68f8d557c9-z8zks-1-640FC208-10 2023-03-14 00:38:32.646335175 +0000 UTC m=+1731918.918798860 Received: from bionic.localdomain (unknown) by geopod-ismtpd-8 (SG) with ESMTP id 6cGs25P-R--M4hAB3QVy7A Tue, 14 Mar 2023 00:38:32.455 +0000 (UTC) From: Jonas Karlman Subject: [PATCH 09/12] mmc: rockchip_dw_mmc: Fix get_mmc_clk return value Date: Tue, 14 Mar 2023 00:38:32 +0000 (UTC) Message-Id: <20230314003755.512696-10-jonas@kwiboo.se> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230314003755.512696-1-jonas@kwiboo.se> References: <20230314003755.512696-1-jonas@kwiboo.se> MIME-Version: 1.0 X-SG-EID: =?us-ascii?Q?TdbjyGynYnRZWhH+7lKUQJL+ZxmxpowvO2O9SQF5CwCVrYgcwUXgU5DKUU3QxA?= =?us-ascii?Q?fZekEeQsTe+RrMu3cja6a0h=2FLNFVHw8JpnKlepK?= =?us-ascii?Q?Fhml5tSfkD5wnAyyfdZ4r=2FTnleuossCKajRRMaB?= =?us-ascii?Q?rBIn37LEt53aCp8nsqRAGs9LWCMv4+k8bYg15l1?= =?us-ascii?Q?WUiG1v4zkKTn70Oe6bmsB6gcYPfI+VT7UJT8F73?= =?us-ascii?Q?LtJo9Jvw8teTTtXqxRGzUadm6j=2FYM3JPQLeLDm?= To: Kever Yang , Simon Glass , Philipp Tomsich , Peng Fan , Jaehoon Chung Cc: Jagan Teki , Eugen Hristev , u-boot@lists.denx.de, Jonas Karlman X-Entity-ID: P7KYpSJvGCELWjBME/J5tg== Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset=us-ascii X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean The get_mmc_clk ops is expected to set a clock rate and return the configured rate as an unsigned value. However, if clk_set_rate fails, e.g. using a fixed rate clock, a negative error value is returned. The mmc core will treat this as a valid unsigned rate and tries to configure a divider based on this bogus clock rate. Use 0 as the return value when setting clock rate fails, the mmc core will configure to use bypass mode instead of using a bogus divider. Signed-off-by: Jonas Karlman --- drivers/mmc/rockchip_dw_mmc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/rockchip_dw_mmc.c b/drivers/mmc/rockchip_dw_mmc.c index 3661ce33143e..72c820ee6330 100644 --- a/drivers/mmc/rockchip_dw_mmc.c +++ b/drivers/mmc/rockchip_dw_mmc.c @@ -52,7 +52,7 @@ static uint rockchip_dwmmc_get_mmc_clk(struct dwmci_host *host, uint freq) ret = clk_set_rate(&priv->clk, freq); if (ret < 0) { debug("%s: err=%d\n", __func__, ret); - return ret; + return 0; } return freq; -- 2.39.2