From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 49C5DC6FD1D for ; Tue, 14 Mar 2023 23:07:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230001AbjCNXHH (ORCPT ); Tue, 14 Mar 2023 19:07:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42948 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229540AbjCNXHF (ORCPT ); Tue, 14 Mar 2023 19:07:05 -0400 Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8E0C12CFD5; Tue, 14 Mar 2023 16:07:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1678835224; x=1710371224; h=from:to:cc:subject:date:message-id; bh=WrrhCRvdXc22LfrfW5RvmTwqb6i5r2ubwQSHJiMjvQE=; b=Dq80RIaqaSINecA0xrtIbjXy4wKht35msa1KXtYjPigzAE+FQ0GAfwG8 dQTF+4atESJ83stEYMfxg5yWs1JTsp1lhqURVwlRfnBW+VFZMFinmQw03 43oX3RS8+IxoCmbxROPKipNSNytFd57lK4ZlueQ7J4jlr50DIZjaqkAxd gD2LNaPj7uCI191cgBkxcd2Lw3hBDblMFde5SPOpLIZgsSc4A3kM7v9Rb HSULqOQcMlgvjddBovFgd+4uckJFYKcv278D8zaroIuONIrmQLCcZpDP1 4+I7FAG4s3MxLUOBBDJV/gzUAK3p5LLGP73Gv7diFHJQAfCV6g+VbEKWj Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10649"; a="339926314" X-IronPort-AV: E=Sophos;i="5.98,261,1673942400"; d="scan'208";a="339926314" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Mar 2023 16:07:04 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10649"; a="743481196" X-IronPort-AV: E=Sophos;i="5.98,261,1673942400"; d="scan'208";a="743481196" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by fmsmga008.fm.intel.com with ESMTP; 14 Mar 2023 16:07:03 -0700 From: Ricardo Neri To: x86@kernel.org Cc: Ricardo Neri , linux-kernel@vger.kernel.org, Ricardo Neri , Srinivas Pandruvada , Len Brown , "Rafael J. Wysocki" , Zhang Rui , Chen Yu , stable@vger.kernel.org Subject: [PATCH] x86/cacheinfo: Define per-CPU num_cache_leaves Date: Tue, 14 Mar 2023 16:16:58 -0700 Message-Id: <20230314231658.30169-1-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Make num_cache_leaves a per-CPU variable. Otherwise, populate_cache_ leaves() fails on systems with asymmetric number of subleaves in CPUID leaf 0x4. Intel Meteor Lake is an example of such a system. Cc: Srinivas Pandruvada Cc: Len Brown Cc: "Rafael J. Wysocki" Cc: Zhang Rui Cc: Chen Yu Cc: stable@vger.kernel.org Reviewed-by: Len Brown Signed-off-by: Ricardo Neri --- After this change, all CPUs will traverse CPUID leaf 0x4 when booted for the first time. On systems with asymmetric cache topologies this is useless work. Creating a list of processor models that have asymmetric cache topologies was considered. The burden of maintaining such list would outweigh the performance benefit of skipping this extra step. --- arch/x86/kernel/cpu/cacheinfo.c | 48 ++++++++++++++++++++------------- 1 file changed, 29 insertions(+), 19 deletions(-) diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinfo.c index 4063e8991211..6ad51657c853 100644 --- a/arch/x86/kernel/cpu/cacheinfo.c +++ b/arch/x86/kernel/cpu/cacheinfo.c @@ -176,7 +176,18 @@ struct _cpuid4_info_regs { struct amd_northbridge *nb; }; -static unsigned short num_cache_leaves; +static DEFINE_PER_CPU(unsigned short, num_cache_leaves); + +static inline unsigned short get_num_cache_leaves(unsigned int cpu) +{ + return per_cpu(num_cache_leaves, cpu); +} + +static inline void +set_num_cache_leaves(unsigned short nr_leaves, unsigned int cpu) +{ + per_cpu(num_cache_leaves, cpu) = nr_leaves; +} /* AMD doesn't have CPUID4. Emulate it here to report the same information to the user. This makes some assumptions about the machine: @@ -716,19 +727,21 @@ void cacheinfo_hygon_init_llc_id(struct cpuinfo_x86 *c, int cpu) void init_amd_cacheinfo(struct cpuinfo_x86 *c) { + unsigned int cpu = c->cpu_index; + if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { - num_cache_leaves = find_num_cache_leaves(c); + set_num_cache_leaves(find_num_cache_leaves(c), cpu); } else if (c->extended_cpuid_level >= 0x80000006) { if (cpuid_edx(0x80000006) & 0xf000) - num_cache_leaves = 4; + set_num_cache_leaves(4, cpu); else - num_cache_leaves = 3; + set_num_cache_leaves(3, cpu); } } void init_hygon_cacheinfo(struct cpuinfo_x86 *c) { - num_cache_leaves = find_num_cache_leaves(c); + set_num_cache_leaves(find_num_cache_leaves(c), c->cpu_index); } void init_intel_cacheinfo(struct cpuinfo_x86 *c) @@ -738,24 +751,21 @@ void init_intel_cacheinfo(struct cpuinfo_x86 *c) unsigned int new_l1d = 0, new_l1i = 0; /* Cache sizes from cpuid(4) */ unsigned int new_l2 = 0, new_l3 = 0, i; /* Cache sizes from cpuid(4) */ unsigned int l2_id = 0, l3_id = 0, num_threads_sharing, index_msb; -#ifdef CONFIG_SMP unsigned int cpu = c->cpu_index; -#endif if (c->cpuid_level > 3) { - static int is_initialized; - - if (is_initialized == 0) { - /* Init num_cache_leaves from boot CPU */ - num_cache_leaves = find_num_cache_leaves(c); - is_initialized++; - } + /* + * There should be at least one leaf. A non-zero value means + * that the number of leaves has been initialized. + */ + if (!get_num_cache_leaves(cpu)) + set_num_cache_leaves(find_num_cache_leaves(c), cpu); /* * Whenever possible use cpuid(4), deterministic cache * parameters cpuid leaf to find the cache details */ - for (i = 0; i < num_cache_leaves; i++) { + for (i = 0; i < get_num_cache_leaves(cpu); i++) { struct _cpuid4_info_regs this_leaf = {}; int retval; @@ -791,14 +801,14 @@ void init_intel_cacheinfo(struct cpuinfo_x86 *c) * Don't use cpuid2 if cpuid4 is supported. For P4, we use cpuid2 for * trace cache */ - if ((num_cache_leaves == 0 || c->x86 == 15) && c->cpuid_level > 1) { + if ((!get_num_cache_leaves(cpu) || c->x86 == 15) && c->cpuid_level > 1) { /* supports eax=2 call */ int j, n; unsigned int regs[4]; unsigned char *dp = (unsigned char *)regs; int only_trace = 0; - if (num_cache_leaves != 0 && c->x86 == 15) + if (get_num_cache_leaves(cpu) && c->x86 == 15) only_trace = 1; /* Number of times to iterate */ @@ -1000,12 +1010,12 @@ int init_cache_level(unsigned int cpu) { struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu); - if (!num_cache_leaves) + if (!get_num_cache_leaves(cpu)) return -ENOENT; if (!this_cpu_ci) return -EINVAL; this_cpu_ci->num_levels = 3; - this_cpu_ci->num_leaves = num_cache_leaves; + this_cpu_ci->num_leaves = get_num_cache_leaves(cpu); return 0; } -- 2.25.1