All of lore.kernel.org
 help / color / mirror / Atom feed
From: Xingyu Wu <xingyu.wu@starfivetech.com>
To: <linux-riscv@lists.infradead.org>, <devicetree@vger.kernel.org>,
	"Michael Turquette" <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	Conor Dooley <conor@kernel.org>,
	"Emil Renner Berthing" <kernel@esmil.dk>
Cc: Rob Herring <robh+dt@kernel.org>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Hal Feng <hal.feng@starfivetech.com>,
	Xingyu Wu <xingyu.wu@starfivetech.com>,
	William Qiu <william.qiu@starfivetech.com>,
	<linux-kernel@vger.kernel.org>, <linux-clk@vger.kernel.org>
Subject: [PATCH v2 6/6] riscv: dts: starfive: jh7110: Add PLL clock node and modify syscrg node
Date: Thu, 16 Mar 2023 11:05:14 +0800	[thread overview]
Message-ID: <20230316030514.137427-7-xingyu.wu@starfivetech.com> (raw)
In-Reply-To: <20230316030514.137427-1-xingyu.wu@starfivetech.com>

Add the PLL clock node for the Starfive JH7110 SoC and
modify the SYSCRG node to add PLL clocks.

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
---
 arch/riscv/boot/dts/starfive/jh7110.dtsi | 16 +++++++++++++---
 1 file changed, 13 insertions(+), 3 deletions(-)

diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 49dd62276b0d..37ccd4600da8 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -461,19 +461,29 @@ syscrg: clock-controller@13020000 {
 				 <&gmac1_rgmii_rxin>,
 				 <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
 				 <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
-				 <&tdm_ext>, <&mclk_ext>;
+				 <&tdm_ext>, <&mclk_ext>,
+				 <&pllclk JH7110_CLK_PLL0_OUT>,
+				 <&pllclk JH7110_CLK_PLL1_OUT>,
+				 <&pllclk JH7110_CLK_PLL2_OUT>;
 			clock-names = "osc", "gmac1_rmii_refin",
 				      "gmac1_rgmii_rxin",
 				      "i2stx_bclk_ext", "i2stx_lrck_ext",
 				      "i2srx_bclk_ext", "i2srx_lrck_ext",
-				      "tdm_ext", "mclk_ext";
+				      "tdm_ext", "mclk_ext",
+				      "pll0_out", "pll1_out", "pll2_out";
 			#clock-cells = <1>;
 			#reset-cells = <1>;
 		};
 
 		sys_syscon: syscon@13030000 {
-			compatible = "starfive,jh7110-sys-syscon", "syscon";
+			compatible = "starfive,jh7110-sys-syscon", "syscon", "simple-mfd";
 			reg = <0x0 0x13030000 0x0 0x1000>;
+
+			pllclk: pll-clock-controller {
+				compatible = "starfive,jh7110-pll";
+				clocks = <&osc>;
+				#clock-cells = <1>;
+			};
 		};
 
 		sysgpio: pinctrl@13040000 {
-- 
2.25.1


WARNING: multiple messages have this Message-ID (diff)
From: Xingyu Wu <xingyu.wu@starfivetech.com>
To: <linux-riscv@lists.infradead.org>, <devicetree@vger.kernel.org>,
	"Michael Turquette" <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	Conor Dooley <conor@kernel.org>,
	"Emil Renner Berthing" <kernel@esmil.dk>
Cc: Rob Herring <robh+dt@kernel.org>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Hal Feng <hal.feng@starfivetech.com>,
	Xingyu Wu <xingyu.wu@starfivetech.com>,
	William Qiu <william.qiu@starfivetech.com>,
	<linux-kernel@vger.kernel.org>, <linux-clk@vger.kernel.org>
Subject: [PATCH v2 6/6] riscv: dts: starfive: jh7110: Add PLL clock node and modify syscrg node
Date: Thu, 16 Mar 2023 11:05:14 +0800	[thread overview]
Message-ID: <20230316030514.137427-7-xingyu.wu@starfivetech.com> (raw)
In-Reply-To: <20230316030514.137427-1-xingyu.wu@starfivetech.com>

Add the PLL clock node for the Starfive JH7110 SoC and
modify the SYSCRG node to add PLL clocks.

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
---
 arch/riscv/boot/dts/starfive/jh7110.dtsi | 16 +++++++++++++---
 1 file changed, 13 insertions(+), 3 deletions(-)

diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 49dd62276b0d..37ccd4600da8 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -461,19 +461,29 @@ syscrg: clock-controller@13020000 {
 				 <&gmac1_rgmii_rxin>,
 				 <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
 				 <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
-				 <&tdm_ext>, <&mclk_ext>;
+				 <&tdm_ext>, <&mclk_ext>,
+				 <&pllclk JH7110_CLK_PLL0_OUT>,
+				 <&pllclk JH7110_CLK_PLL1_OUT>,
+				 <&pllclk JH7110_CLK_PLL2_OUT>;
 			clock-names = "osc", "gmac1_rmii_refin",
 				      "gmac1_rgmii_rxin",
 				      "i2stx_bclk_ext", "i2stx_lrck_ext",
 				      "i2srx_bclk_ext", "i2srx_lrck_ext",
-				      "tdm_ext", "mclk_ext";
+				      "tdm_ext", "mclk_ext",
+				      "pll0_out", "pll1_out", "pll2_out";
 			#clock-cells = <1>;
 			#reset-cells = <1>;
 		};
 
 		sys_syscon: syscon@13030000 {
-			compatible = "starfive,jh7110-sys-syscon", "syscon";
+			compatible = "starfive,jh7110-sys-syscon", "syscon", "simple-mfd";
 			reg = <0x0 0x13030000 0x0 0x1000>;
+
+			pllclk: pll-clock-controller {
+				compatible = "starfive,jh7110-pll";
+				clocks = <&osc>;
+				#clock-cells = <1>;
+			};
 		};
 
 		sysgpio: pinctrl@13040000 {
-- 
2.25.1


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

  parent reply	other threads:[~2023-03-16  3:06 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-03-16  3:05 [PATCH v2 0/6] Add PLL clocks driver for StarFive JH7110 SoC Xingyu Wu
2023-03-16  3:05 ` Xingyu Wu
2023-03-16  3:05 ` [PATCH v2 1/6] dt-bindings: clock: Add StarFive JH7110 PLL clock generator Xingyu Wu
2023-03-16  3:05   ` Xingyu Wu
2023-03-19 12:25   ` Krzysztof Kozlowski
2023-03-19 12:25     ` Krzysztof Kozlowski
2023-03-20  2:41     ` Xingyu Wu
2023-03-20  2:41       ` Xingyu Wu
2023-03-16  3:05 ` [PATCH v2 2/6] clk: starfive: Add StarFive JH7110 PLL clock driver Xingyu Wu
2023-03-16  3:05   ` Xingyu Wu
2023-03-16  3:05 ` [PATCH v2 3/6] dt-bindings: soc: starfive: syscon: Add optional patternProperties Xingyu Wu
2023-03-16  3:05   ` Xingyu Wu
2023-03-19 12:28   ` Krzysztof Kozlowski
2023-03-19 12:28     ` Krzysztof Kozlowski
2023-03-20  3:54     ` Xingyu Wu
2023-03-20  3:54       ` Xingyu Wu
2023-03-20  6:37       ` Krzysztof Kozlowski
2023-03-20  6:37         ` Krzysztof Kozlowski
2023-03-20  7:29         ` Xingyu Wu
2023-03-20  7:29           ` Xingyu Wu
2023-03-20  7:40           ` Krzysztof Kozlowski
2023-03-20  7:40             ` Krzysztof Kozlowski
2023-03-20  8:26             ` Xingyu Wu
2023-03-20  8:26               ` Xingyu Wu
2023-03-20  8:36               ` Krzysztof Kozlowski
2023-03-20  8:36                 ` Krzysztof Kozlowski
2023-03-20  9:16                 ` Xingyu Wu
2023-03-20  9:16                   ` Xingyu Wu
2023-03-16  3:05 ` [PATCH v2 4/6] dt-bindings: clock: jh7110-syscrg: Add PLL clock inputs Xingyu Wu
2023-03-16  3:05   ` Xingyu Wu
2023-03-19 12:25   ` Krzysztof Kozlowski
2023-03-19 12:25     ` Krzysztof Kozlowski
2023-03-16  3:05 ` [PATCH v2 5/6] clk: starfive: jh7110-sys: Modify PLL clocks source Xingyu Wu
2023-03-16  3:05   ` Xingyu Wu
2023-03-16  3:05 ` Xingyu Wu [this message]
2023-03-16  3:05   ` [PATCH v2 6/6] riscv: dts: starfive: jh7110: Add PLL clock node and modify syscrg node Xingyu Wu

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20230316030514.137427-7-xingyu.wu@starfivetech.com \
    --to=xingyu.wu@starfivetech.com \
    --cc=aou@eecs.berkeley.edu \
    --cc=conor@kernel.org \
    --cc=devicetree@vger.kernel.org \
    --cc=hal.feng@starfivetech.com \
    --cc=kernel@esmil.dk \
    --cc=krzysztof.kozlowski+dt@linaro.org \
    --cc=linux-clk@vger.kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-riscv@lists.infradead.org \
    --cc=mturquette@baylibre.com \
    --cc=p.zabel@pengutronix.de \
    --cc=palmer@dabbelt.com \
    --cc=paul.walmsley@sifive.com \
    --cc=robh+dt@kernel.org \
    --cc=sboyd@kernel.org \
    --cc=william.qiu@starfivetech.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.