From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0DC6FC6FD1F for ; Sun, 19 Mar 2023 16:22:55 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 1285C83CB4; Sun, 19 Mar 2023 17:22:53 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="Jcbij9h5"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 4870A84F3E; Sun, 19 Mar 2023 17:22:51 +0100 (CET) Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 6182983AA4 for ; Sun, 19 Mar 2023 17:22:48 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=pali@kernel.org Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 4A11B61068; Sun, 19 Mar 2023 16:22:46 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 602FDC433EF; Sun, 19 Mar 2023 16:22:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1679242965; bh=0Hxssj/oBn4KBOv0vtnB4/5vjrSatDHlKpKXKcddFVk=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=Jcbij9h5V8NMVAz74JGa5VjssFkJytG1HUVhj72MyMa/KwIL5diYQj1ACs1RYtqSx ryCnbu8BFyqP4Bmh6rjQm6UzFsNbqxqAsnTNMWHF8S/qxs47FDwKE9FwdcZZgTz/UC P5wAKstq7avSKnhEYgOT9fjD4++5ofkLnCGEA1ujZJW42uVRewlalyuEGLlwFsJa6X Z2Q/lseko1bS776ZCasm1ngMvW96AFrQKpQW47892fG5KyiOxnWal1/4I0qPZigAFu sY8DpUHUv6HvdRcpZ5WjHS5wx86m4EhBscK4b+GCQ/TtqsciA9ToUor2MHXd1pfUGj U5Cj0e1Go+crQ== Received: by pali.im (Postfix) id 71366622; Sun, 19 Mar 2023 17:22:42 +0100 (CET) Date: Sun, 19 Mar 2023 17:22:42 +0100 From: Pali =?utf-8?B?Um9ow6Fy?= To: Martin Rowe Cc: u-boot@lists.denx.de Subject: Re: [PATCH RFC u-boot-mvebu 0/2] arm: mvebu: Fix eMMC boot Message-ID: <20230319162242.eq5rsxofrrq2ukdg@pali> References: <20230304103851.18965-1-pali@kernel.org> <20230305114634.h6wyi26ohuzuamfg@pali> <20230305160416.xc7wlzmkaociwcf7@pali> <20230306115325.5pfb4lheobjg2tsi@pali> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: User-Agent: NeoMutt/20180716 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean On Sunday 19 March 2023 00:32:01 Martin Rowe wrote: > On Mon, 6 Mar 2023 at 11:53, Pali Rohár wrote: > > > Could you try to print mmc->part_config (ideally as early as possible)? > > > > In SPL mmc->part_config is 255 > In main u-boot at the start of clearfog.c board_init() mmc->part_config is > 255 > In main u-boot at the start of clearfog.c checkboard() mmc->part_config is > 8 (ack: 0, partition_enable: 1, access: 0) 255 is uninitialized value. > If I set partition_enable to 2, I get the same result except the value is > 16 (ack: 0, partition_enable: 2, access: 0) instead of 8 for the last value Try to change "access" bits. > > BootROM - 1.73 > > Booting from MMC > > U-Boot SPL 2023.04-rc3-00159-gd1653548d2-dirty (Mar 19 2023 - 10:05:32 > +1000) > High speed PHY - Version: 2.0 > EEPROM TLV detection failed: Using static config for Clearfog Pro. > Detected Device ID 6828 > board SerDes lanes topology details: > | Lane # | Speed | Type | > -------------------------------- > | 0 | 3 | SATA0 | > | 1 | 0 | SGMII1 | > | 2 | 5 | PCIe1 | > | 3 | 5 | USB3 HOST1 | > | 4 | 5 | PCIe2 | > | 5 | 0 | SGMII2 | > -------------------------------- > High speed PHY - Ended Successfully > mv_ddr: 14.0.0 > DDR3 Training Sequence - Switching XBAR Window to FastPath Window > mv_ddr: completed successfully > spl.c spl_boot_device part_config = 255 > Trying to boot from MMC1 > > > U-Boot 2023.04-rc3-00159-gd1653548d2-dirty (Mar 19 2023 - 10:05:32 +1000) > > SoC: MV88F6828-A0 at 1600 MHz > DRAM: 1 GiB (800 MHz, 32-bit, ECC not enabled) > clearfog.c board_init part_config = 255 > Core: 38 devices, 22 uclasses, devicetree: separate > MMC: mv_sdh: 0 > Loading Environment from MMC... *** Warning - bad CRC, using default > environment > > Model: SolidRun Clearfog A1 > clearfog.c checkboard part_config = 8 > Board: SolidRun Clearfog Pro > Net: > Warning: ethernet@70000 (eth1) using random MAC address - 32:16:0e:b4:d1:d8 > eth1: ethernet@70000 > Warning: ethernet@30000 (eth2) using random MAC address - 72:30:3f:79:07:12 > , eth2: ethernet@30000 > Warning: ethernet@34000 (eth3) using random MAC address - 82:fb:71:23:46:4f > , eth3: ethernet@34000 > Hit any key to stop autoboot: 0 > => mmc partconf 0 > EXT_CSD[179], PARTITION_CONFIG: > BOOT_ACK: 0x0 > BOOT_PARTITION_ENABLE: 0x1 > PARTITION_ACCESS: 0x0 > > > > BootROM - 1.73 > > Booting from MMC > > U-Boot SPL 2023.04-rc3-00159-gd1653548d2-dirty (Mar 19 2023 - 10:05:32 > +1000) > High speed PHY - Version: 2.0 > EEPROM TLV detection failed: Using static config for Clearfog Pro. > Detected Device ID 6828 > board SerDes lanes topology details: > | Lane # | Speed | Type | > -------------------------------- > | 0 | 3 | SATA0 | > | 1 | 0 | SGMII1 | > | 2 | 5 | PCIe1 | > | 3 | 5 | USB3 HOST1 | > | 4 | 5 | PCIe2 | > | 5 | 0 | SGMII2 | > -------------------------------- > High speed PHY - Ended Successfully > mv_ddr: 14.0.0 > DDR3 Training Sequence - Switching XBAR Window to FastPath Window > mv_ddr: completed successfully > spl.c spl_boot_device part_config = 255 > Trying to boot from MMC1 > > > U-Boot 2023.04-rc3-00159-gd1653548d2-dirty (Mar 19 2023 - 10:05:32 +1000) > > SoC: MV88F6828-A0 at 1600 MHz > DRAM: 1 GiB (800 MHz, 32-bit, ECC not enabled) > clearfog.c board_init part_config = 255 > Core: 38 devices, 22 uclasses, devicetree: separate > MMC: mv_sdh: 0 > Loading Environment from MMC... *** Warning - bad CRC, using default > environment > > Model: SolidRun Clearfog A1 > clearfog.c checkboard part_config = 16 > Board: SolidRun Clearfog Pro > Net: > Warning: ethernet@70000 (eth1) using random MAC address - 92:5a:fc:14:e8:f6 > eth1: ethernet@70000 > Warning: ethernet@30000 (eth2) using random MAC address - 42:9c:d8:3a:cb:b2 > , eth2: ethernet@30000 > Warning: ethernet@34000 (eth3) using random MAC address - c6:99:20:f4:02:a0 > , eth3: ethernet@34000 > Hit any key to stop autoboot: 0 > => mmc partconf 0 > EXT_CSD[179], PARTITION_CONFIG: > BOOT_ACK: 0x0 > BOOT_PARTITION_ENABLE: 0x2 > PARTITION_ACCESS: 0x0 > Are both logs from the configuration when SPL+u-boot is stored on Boot0? Could you try to erase Boot0 and store SPL+u-boot to Boot1? I'm interested to see if "access" bits are changed in SPL (before loading main u-boot). > I'm having trouble trying to find the hooks which run between board_init > and checkboard. If you can point me in the right direction I'm happy to > re-run and try to narrow down where the valid values are being set from. Print it directly in drivers/mmc/mmc.c mmc_startup_v4() where mmc->part_config = is set from ext_csd[EXT_CSD_PART_CONF] register. I want to see original value from EXT_CSD_PART_CONF. I do not know which hook is the best, so printing it from mmc.c driver should work better.