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([177.95.89.231]) by smtp.gmail.com with ESMTPSA id ax35-20020a05687c022300b0017243edbe5bsm5586817oac.58.2023.03.22.15.21.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Mar 2023 15:21:30 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH for-8.1 v4 22/25] target/riscv: use misa_ext val in riscv_cpu_validate_extensions() Date: Wed, 22 Mar 2023 19:20:01 -0300 Message-Id: <20230322222004.357013-23-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230322222004.357013-1-dbarboza@ventanamicro.com> References: <20230322222004.357013-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2001:4860:4864:20::33; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x33.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Similar to what we did with riscv_cpu_validate_misa_ext(), let's read all MISA bits from a misa_ext val instead of reading from the cpu->cfg object. This will allow write_misa() to use riscv_cpu_validate_extensions(). Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 25 ++++++++++++++----------- 1 file changed, 14 insertions(+), 11 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ed02332093..0e6b8fb45e 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1109,10 +1109,13 @@ static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp) } /* - * Check consistency between chosen extensions. No changes - * in env->misa_ext are made. + * Check consistency between cpu->cfg extensions and a + * candidate misa_ext value. No changes in env->misa_ext + * are made. */ -static void riscv_cpu_validate_extensions(RISCVCPU *cpu, Error **errp) +static void riscv_cpu_validate_extensions(RISCVCPU *cpu, + uint32_t misa_ext, + Error **errp) { if (cpu->cfg.epmp && !cpu->cfg.pmp) { /* @@ -1123,12 +1126,12 @@ static void riscv_cpu_validate_extensions(RISCVCPU *cpu, Error **errp) return; } - if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) { + if (misa_ext & RVF && !cpu->cfg.ext_icsr) { error_setg(errp, "F extension requires Zicsr"); return; } - if ((cpu->cfg.ext_zawrs) && !cpu->cfg.ext_a) { + if ((cpu->cfg.ext_zawrs) && !(misa_ext & RVA)) { error_setg(errp, "Zawrs extension requires A extension"); return; } @@ -1137,13 +1140,13 @@ static void riscv_cpu_validate_extensions(RISCVCPU *cpu, Error **errp) cpu->cfg.ext_zfhmin = true; } - if (cpu->cfg.ext_zfhmin && !cpu->cfg.ext_f) { + if (cpu->cfg.ext_zfhmin && !(misa_ext & RVF)) { error_setg(errp, "Zfh/Zfhmin extensions require F extension"); return; } /* The V vector extension depends on the Zve64d extension */ - if (cpu->cfg.ext_v) { + if (misa_ext & RVV) { cpu->cfg.ext_zve64d = true; } @@ -1157,12 +1160,12 @@ static void riscv_cpu_validate_extensions(RISCVCPU *cpu, Error **errp) cpu->cfg.ext_zve32f = true; } - if (cpu->cfg.ext_zve64d && !cpu->cfg.ext_d) { + if (cpu->cfg.ext_zve64d && !(misa_ext & RVD)) { error_setg(errp, "Zve64d/V extensions require D extension"); return; } - if (cpu->cfg.ext_zve32f && !cpu->cfg.ext_f) { + if (cpu->cfg.ext_zve32f && !(misa_ext & RVF)) { error_setg(errp, "Zve32f/Zve64f extensions require F extension"); return; } @@ -1195,7 +1198,7 @@ static void riscv_cpu_validate_extensions(RISCVCPU *cpu, Error **errp) error_setg(errp, "Zfinx extension requires Zicsr"); return; } - if (cpu->cfg.ext_f) { + if (misa_ext & RVF) { error_setg(errp, "Zfinx cannot be supported together with F extension"); return; @@ -1367,7 +1370,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) return; } - riscv_cpu_validate_extensions(cpu, &local_err); + riscv_cpu_validate_extensions(cpu, env->misa_ext, &local_err); if (local_err != NULL) { error_propagate(errp, local_err); return; -- 2.39.2