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From: Bill Liu <Bill.Liu@amd.com>
To: <amd-gfx@lists.freedesktop.org>, <Alexander.Deucher@amd.com>,
	<Hawking.Zhang@amd.com>
Cc: Horace.Chen@amd.com, Bill Liu <Bill.Liu@amd.com>, haijun.chang@amd.com
Subject: [PATCH] drm/amdgpu: Adding MES engine reset in SRIOV
Date: Thu, 23 Mar 2023 16:33:38 +0800	[thread overview]
Message-ID: <20230323083338.249117-1-Bill.Liu@amd.com> (raw)

Added AMD_IP_BLOCK_TYPE_MES to the list of engine
under amdgpu_device_ip_reinit_late_sriov, so that MES engine can be
correctly reset in SRIOV environment

Signed-off-by: Bill Liu <Bill.Liu@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 065f5396d0ce..0d9061151048 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3183,7 +3183,8 @@ static int amdgpu_device_ip_reinit_late_sriov(struct amdgpu_device *adev)
 		AMD_IP_BLOCK_TYPE_MES,
 		AMD_IP_BLOCK_TYPE_UVD,
 		AMD_IP_BLOCK_TYPE_VCE,
-		AMD_IP_BLOCK_TYPE_VCN
+		AMD_IP_BLOCK_TYPE_VCN,
+		AMD_IP_BLOCK_TYPE_MES
 	};
 
 	for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
-- 
2.34.1


                 reply	other threads:[~2023-03-23  8:34 UTC|newest]

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