From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 073E4C6FD1C for ; Fri, 24 Mar 2023 12:55:32 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 622AB85D94; Fri, 24 Mar 2023 13:54:58 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="nVPDkQBr"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id BFBB185D38; Fri, 24 Mar 2023 09:05:24 +0100 (CET) Received: from mail-pl1-x635.google.com (mail-pl1-x635.google.com [IPv6:2607:f8b0:4864:20::635]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id DC772859E5 for ; Fri, 24 Mar 2023 09:05:21 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=bhupesh.sharma@linaro.org Received: by mail-pl1-x635.google.com with SMTP id iw3so1150936plb.6 for ; Fri, 24 Mar 2023 01:05:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1679645120; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ioVYMBh4j7uqvv+MuFxSY2BovmrwF/L2CJ1l1ip2cIE=; b=nVPDkQBrmzRhVsHWxNJ4ivRIeQvmyeQmD0BIpgd38aPdC/6yWJkQQnV914kDG1Pt+B PqqvfU/62STBuNi6L1dNLcECz6Hg1tCBeNs6EZ8cd5SL7rP7LIt6FKt1lqEe7WsgMEyG KJayMyB5K9zmje6rVfKPuj+a3f1xUmudEZtXvIoIn49PwqBtIuWJkjFggSdMiEnBsQwX PsD6KuuUBFiWxy9wSUoHlgpvNcsAH580Pg9yb7C+C2ozX/SNIENtEH6jWA4jE3b1rhB8 1/632L9VhCGwUQyyrHNTc00ni1HM6OhbzFUiKxDlZg1wKiJJvRLQIROMD9gLmtZEsGzG VXrg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679645120; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ioVYMBh4j7uqvv+MuFxSY2BovmrwF/L2CJ1l1ip2cIE=; b=a/dafbNlwRdNUSqQpYFzB5hfJjb1/P3m2OFFqIYtsNqKcm7giEwXsObqc2pXuGqVmc h4Tmllje/78E3sPNfENb2aUVj3eysFRXLsoYb2doUTsJUUzgW5FMfB8Slk0hp3voyXsF mZSR+cPK5Mweeol/KtcsNYW/ZxQzE6ipYtKvsMsfvBBT7Ut6zSbQzwaW8nXF2MFGsylY RQ7kIn/m6Ivg6qfX4uiQzpysNFigamSS/WynVI7fcN2tZ1ymdZQtOKqKtpAWrDIx2quN a0RPrAuO1tEqwnnIwxhsgiGgAUAsMKOLZKS6McRuu4Js+hfOvwRVOayXuv6nTkfsWxDQ XJzA== X-Gm-Message-State: AAQBX9dHWnOlCcKxibnu2pbpE73q7G9qhqeiyBNy7apHpHj1ppWzU3fK BsSjtLyrn12KuSsx8Csm/B4Aqm6pMZmC7lU6F1k= X-Google-Smtp-Source: AKy350ac+9xT1kD5lIlmcFHDRDUmRQC3PPEQ1/yXHNN1QIIhqw+KXogNBP6agX4RssCHbJM72GhM+A== X-Received: by 2002:a17:902:ea06:b0:1a2:7d:17ea with SMTP id s6-20020a170902ea0600b001a2007d17eamr2306340plg.56.1679645119892; Fri, 24 Mar 2023 01:05:19 -0700 (PDT) Received: from localhost.localdomain ([2401:4900:1c60:d4c3:8671:83c0:33ae:5a96]) by smtp.gmail.com with ESMTPSA id s22-20020a170902989600b001a04a372fa0sm12205293plp.251.2023.03.24.01.05.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Mar 2023 01:05:19 -0700 (PDT) From: Bhupesh Sharma To: u-boot@lists.denx.de Cc: jh80.chung@samsung.com, peng.fan@nxp.com, rfried.dev@gmail.com, sjg@chromium.org, trini@konsulko.com, dsankouski@gmail.com, bhupesh.linux@gmail.com, bhupesh.sharma@linaro.org Subject: [PATCH 2/5] clocks: qcom: Add clock driver for SM6115 SoC Date: Fri, 24 Mar 2023 13:34:15 +0530 Message-Id: <20230324080418.3856409-3-bhupesh.sharma@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230324080418.3856409-1-bhupesh.sharma@linaro.org> References: <20230324080418.3856409-1-bhupesh.sharma@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Mailman-Approved-At: Fri, 24 Mar 2023 13:54:51 +0100 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Currently the SM6115 clock driver initializes clocks for debug UART only. Along with this import "qcom,gcc-sm6115.h" header from Linux mainline to support DT bindings. Signed-off-by: Bhupesh Sharma --- arch/arm/mach-snapdragon/Makefile | 1 + arch/arm/mach-snapdragon/clock-qrb4210-rb2.c | 110 +++++++++++++++++++ arch/arm/mach-snapdragon/clock-snapdragon.c | 1 + arch/arm/mach-snapdragon/clock-snapdragon.h | 2 + 4 files changed, 114 insertions(+) create mode 100644 arch/arm/mach-snapdragon/clock-qrb4210-rb2.c diff --git a/arch/arm/mach-snapdragon/Makefile b/arch/arm/mach-snapdragon/Makefile index cbaaf23f6b..23aa1a974c 100644 --- a/arch/arm/mach-snapdragon/Makefile +++ b/arch/arm/mach-snapdragon/Makefile @@ -19,3 +19,4 @@ obj-y += pinctrl-qcs404.o obj-y += pinctrl-sdm845.o obj-$(CONFIG_TARGET_QCS404EVB) += clock-qcs404.o obj-$(CONFIG_TARGET_QCS404EVB) += sysmap-qcs404.o +obj-$(CONFIG_TARGET_QRB4210RB2) += clock-qrb4210-rb2.o diff --git a/arch/arm/mach-snapdragon/clock-qrb4210-rb2.c b/arch/arm/mach-snapdragon/clock-qrb4210-rb2.c new file mode 100644 index 0000000000..d67c69b320 --- /dev/null +++ b/arch/arm/mach-snapdragon/clock-qrb4210-rb2.c @@ -0,0 +1,110 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Clock drivers for Qualcomm SM6115 + * + * (C) Copyright 2023 Bhupesh Sharma + * + * Based on Kernel driver, simplified + */ + +#include +#include +#include +#include +#include +#include +#include +#include "clock-snapdragon.h" + +#include + +/* GPLL clock control registers */ +#define GPLL0_STATUS_ACTIVE BIT(31) + +#define GCC_GLOBAL_EN_BASE (0x84000) +#define GCC_CLOBAL_PERIPHERALS_EN BIT(5) + +#define GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1 (0x7900C) + +#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } + +struct freq_tbl { + uint freq; + uint src; + u8 pre_div; + u16 m; + u16 n; +}; + +static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { + F(7372800, CFG_CLK_SRC_GPLL0_OUT_AUX2, 1, 384, 15625), + F(14745600, CFG_CLK_SRC_GPLL0_OUT_AUX2, 1, 768, 15625), + F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0), + F(29491200, CFG_CLK_SRC_GPLL0_OUT_AUX2, 1, 1536, 15625), + F(32000000, CFG_CLK_SRC_GPLL0_OUT_AUX2, 1, 8, 75), + F(48000000, CFG_CLK_SRC_GPLL0_OUT_AUX2, 1, 4, 25), + F(64000000, CFG_CLK_SRC_GPLL0_OUT_AUX2, 1, 16, 75), + F(75000000, CFG_CLK_SRC_GPLL0_OUT_AUX2, 4, 0, 0), + F(80000000, CFG_CLK_SRC_GPLL0_OUT_AUX2, 1, 4, 15), + F(96000000, CFG_CLK_SRC_GPLL0_OUT_AUX2, 1, 8, 25), + F(100000000, CFG_CLK_SRC_GPLL0_OUT_AUX2, 3, 0, 0), + F(102400000, CFG_CLK_SRC_GPLL0_OUT_AUX2, 1, 128, 375), + F(112000000, CFG_CLK_SRC_GPLL0_OUT_AUX2, 1, 28, 75), + F(117964800, CFG_CLK_SRC_GPLL0_OUT_AUX2, 1, 6144, 15625), + F(120000000, CFG_CLK_SRC_GPLL0_OUT_AUX2, 2.5, 0, 0), + F(128000000, CFG_CLK_SRC_GPLL6_OUT_MAIN, 3, 0, 0), + { } +}; + +static const struct bcr_regs uart4_regs = { + .cfg_rcgr = UART4_APPS_CFG_RCGR, + .cmd_rcgr = UART4_APPS_CMD_RCGR, + .M = UART4_APPS_M, + .N = UART4_APPS_N, + .D = UART4_APPS_D, +}; + +const struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, uint rate) +{ + if (!f) + return NULL; + + if (!f->freq) + return f; + + for (; f->freq; f++) + if (rate <= f->freq) + return f; + + /* Default to our fastest rate */ + return f - 1; +} + +static int clk_init_uart(struct msm_clk_priv *priv, uint rate) +{ + const struct freq_tbl *freq = qcom_find_freq(ftbl_gcc_qupv3_wrap0_s0_clk_src, rate); + + clk_rcg_set_rate_mnd(priv->base, &uart4_regs, + freq->pre_div, freq->m, freq->n, freq->src); + + return 0; +} + +ulong msm_set_rate(struct clk *clk, ulong rate) +{ + struct msm_clk_priv *priv = dev_get_priv(clk->dev); + + switch (clk->id) { + case GCC_QUPV3_WRAP0_S4_CLK: /* UART4 */ + return clk_init_uart(priv, rate); + default: + return 0; + } + + return 0; +} + +int msm_enable(struct clk *clk) +{ + return 0; +} diff --git a/arch/arm/mach-snapdragon/clock-snapdragon.c b/arch/arm/mach-snapdragon/clock-snapdragon.c index 0ac45dce9a..f306fd5b20 100644 --- a/arch/arm/mach-snapdragon/clock-snapdragon.c +++ b/arch/arm/mach-snapdragon/clock-snapdragon.c @@ -167,6 +167,7 @@ static const struct udevice_id msm_clk_ids[] = { { .compatible = "qcom,gcc-msm8996" }, { .compatible = "qcom,gcc-apq8096" }, { .compatible = "qcom,gcc-sdm845" }, + { .compatible = "qcom,gcc-sm6115" }, { .compatible = "qcom,gcc-qcs404" }, { } }; diff --git a/arch/arm/mach-snapdragon/clock-snapdragon.h b/arch/arm/mach-snapdragon/clock-snapdragon.h index c90bbefa58..9e520dbbce 100644 --- a/arch/arm/mach-snapdragon/clock-snapdragon.h +++ b/arch/arm/mach-snapdragon/clock-snapdragon.h @@ -10,6 +10,8 @@ #define CFG_CLK_SRC_CXO (0 << 8) #define CFG_CLK_SRC_GPLL0 (1 << 8) #define CFG_CLK_SRC_GPLL0_EVEN (6 << 8) +#define CFG_CLK_SRC_GPLL0_OUT_AUX2 (2 << 8) +#define CFG_CLK_SRC_GPLL6_OUT_MAIN (4 << 8) #define CFG_CLK_SRC_MASK (7 << 8) struct pll_vote_clk { -- 2.38.1