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[87.0.102.254]) by smtp.gmail.com with ESMTPSA id 15-20020a508e4f000000b004fa99a22c3bsm15478850edx.61.2023.03.28.00.33.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Mar 2023 00:33:47 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Vincent Mailhol , Rob Herring , Amarula patchwork , michael@amarulasolutions.com, Marc Kleine-Budde , Alexandre Torgue , Krzysztof Kozlowski , Dario Binacchi , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH v10 3/5] ARM: dts: stm32: add CAN support on stm32f429 Date: Tue, 28 Mar 2023 09:33:26 +0200 Message-Id: <20230328073328.3949796-4-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20230328073328.3949796-1-dario.binacchi@amarulasolutions.com> References: <20230328073328.3949796-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add support for bxcan (Basic eXtended CAN controller) to STM32F429. The chip contains two CAN peripherals, CAN1 the primary and CAN2 the secondary, that share some of the required logic like clock and filters. This means that the secondary CAN can't be used without the primary CAN. Signed-off-by: Dario Binacchi --- (no changes since v9) Changes in v9: - Replace master/slave terms with primary/secondary. Changes in v6: - move can1 node before gcan to keep ordering by address. Changes in v4: - Replace the node can@40006400 (compatible "st,stm32f4-bxcan-core") with the gcan@40006600 node ("sysnode" compatible). The gcan node contains clocks and memory addresses shared by the two can nodes of which it's no longer the parent. - Add to can nodes the "st,gcan" property (global can memory) which references the gcan@40006600 node ("sysnode compatibble). Changes in v3: - Remove 'Dario Binacchi ' SOB. - Add "clocks" to can@0 node. arch/arm/boot/dts/stm32f429.dtsi | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi index c31ceb821231..c9e05e3540d6 100644 --- a/arch/arm/boot/dts/stm32f429.dtsi +++ b/arch/arm/boot/dts/stm32f429.dtsi @@ -362,6 +362,35 @@ i2c3: i2c@40005c00 { status = "disabled"; }; + can1: can@40006400 { + compatible = "st,stm32f4-bxcan"; + reg = <0x40006400 0x200>; + interrupts = <19>, <20>, <21>, <22>; + interrupt-names = "tx", "rx0", "rx1", "sce"; + resets = <&rcc STM32F4_APB1_RESET(CAN1)>; + clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>; + st,can-primary; + st,gcan = <&gcan>; + status = "disabled"; + }; + + gcan: gcan@40006600 { + compatible = "st,stm32f4-gcan", "syscon"; + reg = <0x40006600 0x200>; + clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>; + }; + + can2: can@40006800 { + compatible = "st,stm32f4-bxcan"; + reg = <0x40006800 0x200>; + interrupts = <63>, <64>, <65>, <66>; + interrupt-names = "tx", "rx0", "rx1", "sce"; + resets = <&rcc STM32F4_APB1_RESET(CAN2)>; + clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN2)>; + st,gcan = <&gcan>; + status = "disabled"; + }; + dac: dac@40007400 { compatible = "st,stm32f4-dac-core"; reg = <0x40007400 0x400>; -- 2.32.0 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B5A54C761A6 for ; Tue, 28 Mar 2023 07:34:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=oY8c6RtHKixOSGuZiqlFjLbIZCoGQFS99Xoke6/GJWc=; b=uozs8zOiAUnxo2 L+oGIrBOgd05Iq/g74ggKqqpxJPBk1KCVMz6j0l7OLZnZ1RbRd4kty3IR88SbczCeuiNpk/VbwIvD E4Z0g1vgCsNuFBw52z+WiMlKkqB9jXQbNqcGIsz/BEXEOgZXI37Y8VUwgO9Pb8z8uKAhoYe2Kvhv+ zcRyGyBKU2L1C+LM/xmyOjGE5klf/lvB8Xs1LxlaJjsji2kcVqHXw7SfqEhXRHnYTWZPlVU6CGqui M1X8uV1I0j1Y/k0WtQNVn8ibiVtjNQJIFxi0mqlkIbWa3iHdcs1glsXNpCmLuSrdSQNnGT3AfCckW uPH//htuTQent86hdhpw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1ph3qD-00DSaf-1f; Tue, 28 Mar 2023 07:34:01 +0000 Received: from mail-ed1-x534.google.com ([2a00:1450:4864:20::534]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1ph3q1-00DSSh-1q for linux-arm-kernel@lists.infradead.org; Tue, 28 Mar 2023 07:33:53 +0000 Received: by mail-ed1-x534.google.com with SMTP id i5so45993136eda.0 for ; Tue, 28 Mar 2023 00:33:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1679988828; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2+OmgATyAVN/2E72/iiXhgNbt/jehihFpqYxcu4ydlU=; b=Jkq1icJEBGpJzWE3a+ydM2EXTLlKYwWHnWFUygAagMjBSNS6rgEOOj/KGQyeQ+mRb1 1ZCA3bwF/hz9WpdoFQaK3MAQiwsnMuC/FFA28ORzEcKygJQtWVFg1gQ16jQRKybxd27Y Rjorhs+fyynAn9r36WF7etT+lSKs2V+/dnesI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679988828; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2+OmgATyAVN/2E72/iiXhgNbt/jehihFpqYxcu4ydlU=; b=D1FDl4VGSBpLn+IpE4Q8zLbT4mGWu59uUfGPLT5naPN8Ob0yedmVhGmxZ55PGD1a7o 39t0QXbF2qCD15bYgQSmRx5rUbLrWHuudH9IGo68XjieiTeIfQ/vyvzK6mvECxpPD0ji ThOFLGAKvolTcGTls8gf9YhqsLbgPqwOouaz42+vmv5WXTn6EXLbiUbWevBJ/pBD8K5I Rr86Luvves8RcXqAt3F+DEejncDlfCbrziqhFDG6pIlA3WnruvP0joKUmlthzYBA5naA iamTzBxqVQcfvrCUKy2lkHbuhxcqUfSVWNtbP4oYkAMKGhq1PiyQ7ha+N1uyx7DFuZB1 /m/w== X-Gm-Message-State: AAQBX9fme413UpXl6ddZCiQptRa+4HFBuD9yCkaPTamFLbhdyvLDIGqJ bDUG0EQjGYXAYEY7zhaoJ/OVgw== X-Google-Smtp-Source: AKy350b/J4ht0zqALGVEyDhlsi9kU5K82wFoT3CC1p9mmKbTwqqU3WrYl1fOHJnUUa9g1cEOkRcMAQ== X-Received: by 2002:a17:906:b351:b0:931:d36f:8965 with SMTP id cd17-20020a170906b35100b00931d36f8965mr16661879ejb.13.1679988828000; Tue, 28 Mar 2023 00:33:48 -0700 (PDT) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-87-0-102-254.retail.telecomitalia.it. [87.0.102.254]) by smtp.gmail.com with ESMTPSA id 15-20020a508e4f000000b004fa99a22c3bsm15478850edx.61.2023.03.28.00.33.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Mar 2023 00:33:47 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Vincent Mailhol , Rob Herring , Amarula patchwork , michael@amarulasolutions.com, Marc Kleine-Budde , Alexandre Torgue , Krzysztof Kozlowski , Dario Binacchi , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH v10 3/5] ARM: dts: stm32: add CAN support on stm32f429 Date: Tue, 28 Mar 2023 09:33:26 +0200 Message-Id: <20230328073328.3949796-4-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20230328073328.3949796-1-dario.binacchi@amarulasolutions.com> References: <20230328073328.3949796-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230328_003349_634238_15E240DA X-CRM114-Status: GOOD ( 13.66 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add support for bxcan (Basic eXtended CAN controller) to STM32F429. The chip contains two CAN peripherals, CAN1 the primary and CAN2 the secondary, that share some of the required logic like clock and filters. This means that the secondary CAN can't be used without the primary CAN. Signed-off-by: Dario Binacchi --- (no changes since v9) Changes in v9: - Replace master/slave terms with primary/secondary. Changes in v6: - move can1 node before gcan to keep ordering by address. Changes in v4: - Replace the node can@40006400 (compatible "st,stm32f4-bxcan-core") with the gcan@40006600 node ("sysnode" compatible). The gcan node contains clocks and memory addresses shared by the two can nodes of which it's no longer the parent. - Add to can nodes the "st,gcan" property (global can memory) which references the gcan@40006600 node ("sysnode compatibble). Changes in v3: - Remove 'Dario Binacchi ' SOB. - Add "clocks" to can@0 node. arch/arm/boot/dts/stm32f429.dtsi | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi index c31ceb821231..c9e05e3540d6 100644 --- a/arch/arm/boot/dts/stm32f429.dtsi +++ b/arch/arm/boot/dts/stm32f429.dtsi @@ -362,6 +362,35 @@ i2c3: i2c@40005c00 { status = "disabled"; }; + can1: can@40006400 { + compatible = "st,stm32f4-bxcan"; + reg = <0x40006400 0x200>; + interrupts = <19>, <20>, <21>, <22>; + interrupt-names = "tx", "rx0", "rx1", "sce"; + resets = <&rcc STM32F4_APB1_RESET(CAN1)>; + clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>; + st,can-primary; + st,gcan = <&gcan>; + status = "disabled"; + }; + + gcan: gcan@40006600 { + compatible = "st,stm32f4-gcan", "syscon"; + reg = <0x40006600 0x200>; + clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>; + }; + + can2: can@40006800 { + compatible = "st,stm32f4-bxcan"; + reg = <0x40006800 0x200>; + interrupts = <63>, <64>, <65>, <66>; + interrupt-names = "tx", "rx0", "rx1", "sce"; + resets = <&rcc STM32F4_APB1_RESET(CAN2)>; + clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN2)>; + st,gcan = <&gcan>; + status = "disabled"; + }; + dac: dac@40007400 { compatible = "st,stm32f4-dac-core"; reg = <0x40007400 0x400>; -- 2.32.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel