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DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Mar 2023 16:05:17.1254 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8e93145f-dca0-4edc-18bd-08db306f638e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT042.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5119 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alex Deucher , Felix Kuehling , Christian Koenig , Arvind Yadav , Shashank Sharma Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" From: Arvind Yadav This patch: - adds some new parameters defined for the gfx usermode queues use cases in the v11_mqd_struct. - sets those parametes with the respective allocated gpu context space addresses. Cc: Alex Deucher Cc: Christian Koenig Cc: Shashank Sharma Signed-off-by: Arvind Yadav --- .../drm/amd/amdgpu/amdgpu_userqueue_gfx_v11.c | 21 ++++++++++++++++++- drivers/gpu/drm/amd/include/v11_structs.h | 16 +++++++------- 2 files changed, 28 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue_gfx_v11.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue_gfx_v11.c index 52de96727f98..39e90ea32fcb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue_gfx_v11.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue_gfx_v11.c @@ -22,6 +22,7 @@ */ #include "amdgpu.h" #include "amdgpu_userqueue.h" +#include "v11_structs.h" #define AMDGPU_USERQ_PROC_CTX_SZ PAGE_SIZE #define AMDGPU_USERQ_GANG_CTX_SZ PAGE_SIZE @@ -68,6 +69,22 @@ static void amdgpu_userq_gfx_v11_destroy_ctx_space(struct amdgpu_userq_mgr *uq_m &ctx->cpu_ptr); } +static void +amdgpu_userq_set_ctx_space(struct amdgpu_userq_mgr *uq_mgr, + struct amdgpu_usermode_queue *queue) +{ + struct v11_gfx_mqd *mqd = queue->mqd.cpu_ptr; + + mqd->shadow_base_lo = queue->shadow_ctx_gpu_addr & 0xfffffffc; + mqd->shadow_base_hi = upper_32_bits(queue->shadow_ctx_gpu_addr); + + mqd->gds_bkup_base_lo = queue->gds_ctx_gpu_addr & 0xfffffffc; + mqd->gds_bkup_base_hi = upper_32_bits(queue->gds_ctx_gpu_addr); + + mqd->fw_work_area_base_lo = queue->fw_ctx_gpu_addr & 0xfffffffc; + mqd->fw_work_area_base_lo = upper_32_bits(queue->fw_ctx_gpu_addr); +} + static int amdgpu_userq_gfx_v11_mqd_create(struct amdgpu_userq_mgr *uq_mgr, struct amdgpu_usermode_queue *queue) { @@ -104,12 +121,14 @@ amdgpu_userq_gfx_v11_mqd_create(struct amdgpu_userq_mgr *uq_mgr, struct amdgpu_u queue->userq_prop.use_doorbell = true; queue->userq_prop.mqd_gpu_addr = mqd->gpu_addr; r = gfx_v11_mqd->init_mqd(adev, (void *)mqd->cpu_ptr, &queue->userq_prop); - amdgpu_bo_unreserve(mqd->obj); if (r) { + amdgpu_bo_unreserve(mqd->obj); DRM_ERROR("Failed to init MQD for queue\n"); goto free_ctx; } + amdgpu_userq_set_ctx_space(uq_mgr, queue); + amdgpu_bo_unreserve(mqd->obj); DRM_DEBUG_DRIVER("MQD for queue %d created\n", queue->queue_id); return 0; diff --git a/drivers/gpu/drm/amd/include/v11_structs.h b/drivers/gpu/drm/amd/include/v11_structs.h index b8ff7456ae0b..f8008270f813 100644 --- a/drivers/gpu/drm/amd/include/v11_structs.h +++ b/drivers/gpu/drm/amd/include/v11_structs.h @@ -25,14 +25,14 @@ #define V11_STRUCTS_H_ struct v11_gfx_mqd { - uint32_t reserved_0; // offset: 0 (0x0) - uint32_t reserved_1; // offset: 1 (0x1) - uint32_t reserved_2; // offset: 2 (0x2) - uint32_t reserved_3; // offset: 3 (0x3) - uint32_t reserved_4; // offset: 4 (0x4) - uint32_t reserved_5; // offset: 5 (0x5) - uint32_t reserved_6; // offset: 6 (0x6) - uint32_t reserved_7; // offset: 7 (0x7) + uint32_t shadow_base_lo; // offset: 0 (0x0) + uint32_t shadow_base_hi; // offset: 1 (0x1) + uint32_t gds_bkup_base_lo; // offset: 2 (0x2) + uint32_t gds_bkup_base_hi; // offset: 3 (0x3) + uint32_t fw_work_area_base_lo; // offset: 4 (0x4) + uint32_t fw_work_area_base_hi; // offset: 5 (0x5) + uint32_t shadow_initialized; // offset: 6 (0x6) + uint32_t ib_vmid; // offset: 7 (0x7) uint32_t reserved_8; // offset: 8 (0x8) uint32_t reserved_9; // offset: 9 (0x9) uint32_t reserved_10; // offset: 10 (0xA) -- 2.40.0