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client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C From: Parav Pandit To: , , CC: , , Parav Pandit , Satananda Burla Date: Fri, 31 Mar 2023 01:58:32 +0300 Message-ID: <20230330225834.506969-10-parav@nvidia.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20230330225834.506969-1-parav@nvidia.com> References: <20230330225834.506969-1-parav@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.126.231.37] X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT086:EE_|DM4PR12MB5326:EE_ X-MS-Office365-Filtering-Correlation-Id: 278c845a-a69a-473e-c941-08db31726d1f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: lW/efizUFAf1ozChKMQuSsd56F+oQD2XW15mlz67RVhBRRRNO3CTBHFHzCHLLtoqQmuMLS8ikeofAG+0CXWiG9YJrnca0gOdf6/kpxj0Jh7YJJ9xP1eGkzzAei9dfnMj0EINBlTdm0Lb4wbb+ICn2PeYs3gfu5rWPIqtHVFmy+jpJoJb6NFaJdAugv/E8kigGeEalcXkkwA5EGLSmrkTMxAaWhEuwVetuBOHvkFwSe4V1/CwyYEo/NPYptN6zMggxEc/LGn9F+gTfmUrNuaI+Ze4vdCZXQAFzhdWwUYPmIUuf54hi4VRkijNP9PeNlb9NCAyl17dTf3AHMcBz+2/Cs/H4IBMksgxS/I38zNfhxMH76T/+rRsFfLUvH0azbu4mpi2y7h/O+OBVRufarYyu36SF7xsLXoGSWB4n5x8HyO4WcxzKCTNoYwbzMWO2B7jH5o/TnFLZrIcBw+oufD40XTHkzGWnl0o9AM6n9IVPoS+3dbP0NYbbhGz+UCU/Pi/j/0gI6hKqSb1tdyxRbHTphgTDb5GNNYQjVq/CNDQaoCqr/o+pWTDAon9YV/6xg9WvQMuqm54sJmEOGflITYZqWqBG2JQPaTgRKjNuddaoFVGihbIPyTej33k7/C0GtwAXoEmhkpDhHgkVNAe/6I7iAyfU/Q+UNAgDQMpDbxqp1xVbacYyShi5SdMlGz8ldLC4joCijMrLJkouTeG9RN2e3YOHsNyiqOfA+idAQRmQvGgiZE2d9ZtL6YtdUTG2UIxfNdpUlhQLqNkWblTpcFRpvKpeSahZ/9c3JknHuaP9Eo= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230028)(4636009)(136003)(376002)(396003)(346002)(39860400002)(451199021)(36840700001)(46966006)(40470700004)(110136005)(5660300002)(8936002)(2906002)(316002)(40480700001)(186003)(70206006)(41300700001)(40460700003)(86362001)(26005)(70586007)(54906003)(8676002)(4326008)(36756003)(478600001)(356005)(7636003)(2616005)(16526019)(1076003)(82740400003)(82310400005)(83380400001)(336012)(6666004)(47076005)(36860700001)(426003)(34020700004);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Mar 2023 22:59:32.8324 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 278c845a-a69a-473e-c941-08db31726d1f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT086.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5326 Subject: [virtio-dev] [PATCH 09/11] transport-pci: Describe PCI MMR dev config registers Legacy virtio configuration registers and adjacent device configuration registers are located somewhere in a memory BAR. A new capability supplies the location of these registers which a driver can use to map I/O access to legacy memory mapped registers. This gives the ability to locate legacy registers in either the existing memory BAR or as completely new BAR at BAR 0. A below example diagram attempts to depicts it in an existing memory BAR. +------------------------------+ |Transitional | |MMR SRIOV VF | | | ++---------------+ | ||dev_id = | | ||{0x10f9-0x10ff}| | |+---------------+ | | | ++--------------------+ | || PCIe ext cap = 0xB | | || cfg_type = 10 | | || offset = 0x1000 | | || bar = A {0..5}| | |+--|-----------------+ | | | | | | | | | +-------------------+ | | | | Memory BAR = A | | | | | | | | +------>+--------------+ | | | | |legacy virtio | | | | | |+ dev cfg | | | | | |registers | | | | | +--------------+ | | | +-----------------+ | | +------------------------------+ Co-developed-by: Satananda Burla Signed-off-by: Parav Pandit --- transport-pci.tex | 33 +++++++++++++++++++++++++++++++-- 1 file changed, 31 insertions(+), 2 deletions(-) diff --git a/transport-pci.tex b/transport-pci.tex index aeda4a1..55a6aa0 100644 --- a/transport-pci.tex +++ b/transport-pci.tex @@ -168,6 +168,7 @@ \subsection{Virtio Structure PCI Capabilities}\label{sec:Virtio Transport Option \item ISR Status \item Device-specific configuration (optional) \item PCI configuration access +\item Legacy memory mapped configuration registers (optional) \end{itemize} Each structure can be mapped by a Base Address register (BAR) belonging to @@ -228,6 +229,8 @@ \subsection{Virtio Structure PCI Capabilities}\label{sec:Virtio Transport Option #define VIRTIO_PCI_CAP_SHARED_MEMORY_CFG 8 /* Vendor-specific data */ #define VIRTIO_PCI_CAP_VENDOR_CFG 9 +/* Legacy configuration registers capability */ +#define VIRTIO_PCI_CAP_LEGACY_MMR_CFG 10 \end{lstlisting} Any other value is reserved for future use. @@ -682,6 +685,18 @@ \subsubsection{Common configuration structure layout}\label{sec:Virtio Transport Configuration Space / Legacy Interface: Device Configuration Space}~\nameref{sec:Basic Facilities of a Virtio Device / Device Configuration Space / Legacy Interface: Device Configuration Space} for workarounds. +\paragraph{Transitional MMR Interface: A Note on Configuration Registers} +\label{sec:Virtio Transport Options / Virtio Over PCI Bus / Virtio Structure PCI Capabilities / Common configuration structure layout / Transitional MMR Interface: A Note on Configuration Registers} + +The transitional MMR device MUST present legacy virtio registers +consisting of legacy common configuration registers followed by +legacy device specific configuration registers described in section +\ref{sec:Virtio Transport Options / Virtio Over PCI Bus / Virtio Structure PCI Capabilities / Common configuration structure layout / Legacy Interfaces: A Note on Configuration Registers} +in a memory region PCI BAR. + +The transitional MMR device MUST provide the location of the +legacy virtio configuration registers using a legacy memory mapped +registers capability described in section \ref{sec:Virtio Transport Options / Virtio Over PCI Bus / Virtio Structure PCI Capabilities / Transitional MMR Interface: Legacy Memory Mapped Configuration Registers Capability}. \subsubsection{Notification structure layout}\label{sec:Virtio Transport Options / Virtio Over PCI Bus / PCI Device Layout / Notification capability} @@ -956,9 +971,23 @@ \subsubsection{PCI configuration access capability}\label{sec:Virtio Transport O specified by some other Virtio Structure PCI Capability of type other than \field{VIRTIO_PCI_CAP_PCI_CFG}. +\subsubsection{Transitional MMR Interface: Legacy Memory Mapped Configuration Registers Capability} +\label{sec:Virtio Transport Options / Virtio Over PCI Bus / Virtio Structure PCI Capabilities / Transitional MMR Interface: Legacy Memory Mapped Configuration Registers Capability} + +The optional VIRTIO_PCI_CAP_LEGACY_MMR_CFG capability defines +the location of the legacy virtio configuration registers +followed by legacy device specific configuration registers in +the memory region BAR for the transitional MMR device. + +The \field{cap.offset} MUST be 4-byte aligned. +The \field{cap.offset} SHOULD be 4KBytes aligned and +\field{cap.length} SHOULD be 4KBytes. + +The transitional MMR device MUST present a legacy configuration +memory mapped registers capability using \field{virtio_pcie_ext_cap}. + \subsubsection{Legacy Interface: A Note on Feature Bits} -\label{sec:Virtio Transport Options / Virtio Over PCI Bus / -Virtio Structure PCI Capabilities / Legacy Interface: A Note on Feature Bits} +\label{sec:Virtio Transport Options / Virtio Over PCI Bus / Virtio Structure PCI Capabilities / Legacy Interface: A Note on Feature Bits} Only Feature Bits 0 to 31 are accessible through the Legacy Interface. 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Mar 2023 22:59:32.8324 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 278c845a-a69a-473e-c941-08db31726d1f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT086.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5326 Subject: [virtio-comment] [PATCH 09/11] transport-pci: Describe PCI MMR dev config registers Legacy virtio configuration registers and adjacent device configuration registers are located somewhere in a memory BAR. A new capability supplies the location of these registers which a driver can use to map I/O access to legacy memory mapped registers. This gives the ability to locate legacy registers in either the existing memory BAR or as completely new BAR at BAR 0. A below example diagram attempts to depicts it in an existing memory BAR. +------------------------------+ |Transitional | |MMR SRIOV VF | | | ++---------------+ | ||dev_id = | | ||{0x10f9-0x10ff}| | |+---------------+ | | | ++--------------------+ | || PCIe ext cap = 0xB | | || cfg_type = 10 | | || offset = 0x1000 | | || bar = A {0..5}| | |+--|-----------------+ | | | | | | | | | +-------------------+ | | | | Memory BAR = A | | | | | | | | +------>+--------------+ | | | | |legacy virtio | | | | | |+ dev cfg | | | | | |registers | | | | | +--------------+ | | | +-----------------+ | | +------------------------------+ Co-developed-by: Satananda Burla Signed-off-by: Parav Pandit --- transport-pci.tex | 33 +++++++++++++++++++++++++++++++-- 1 file changed, 31 insertions(+), 2 deletions(-) diff --git a/transport-pci.tex b/transport-pci.tex index aeda4a1..55a6aa0 100644 --- a/transport-pci.tex +++ b/transport-pci.tex @@ -168,6 +168,7 @@ \subsection{Virtio Structure PCI Capabilities}\label{sec:Virtio Transport Option \item ISR Status \item Device-specific configuration (optional) \item PCI configuration access +\item Legacy memory mapped configuration registers (optional) \end{itemize} Each structure can be mapped by a Base Address register (BAR) belonging to @@ -228,6 +229,8 @@ \subsection{Virtio Structure PCI Capabilities}\label{sec:Virtio Transport Option #define VIRTIO_PCI_CAP_SHARED_MEMORY_CFG 8 /* Vendor-specific data */ #define VIRTIO_PCI_CAP_VENDOR_CFG 9 +/* Legacy configuration registers capability */ +#define VIRTIO_PCI_CAP_LEGACY_MMR_CFG 10 \end{lstlisting} Any other value is reserved for future use. @@ -682,6 +685,18 @@ \subsubsection{Common configuration structure layout}\label{sec:Virtio Transport Configuration Space / Legacy Interface: Device Configuration Space}~\nameref{sec:Basic Facilities of a Virtio Device / Device Configuration Space / Legacy Interface: Device Configuration Space} for workarounds. +\paragraph{Transitional MMR Interface: A Note on Configuration Registers} +\label{sec:Virtio Transport Options / Virtio Over PCI Bus / Virtio Structure PCI Capabilities / Common configuration structure layout / Transitional MMR Interface: A Note on Configuration Registers} + +The transitional MMR device MUST present legacy virtio registers +consisting of legacy common configuration registers followed by +legacy device specific configuration registers described in section +\ref{sec:Virtio Transport Options / Virtio Over PCI Bus / Virtio Structure PCI Capabilities / Common configuration structure layout / Legacy Interfaces: A Note on Configuration Registers} +in a memory region PCI BAR. + +The transitional MMR device MUST provide the location of the +legacy virtio configuration registers using a legacy memory mapped +registers capability described in section \ref{sec:Virtio Transport Options / Virtio Over PCI Bus / Virtio Structure PCI Capabilities / Transitional MMR Interface: Legacy Memory Mapped Configuration Registers Capability}. \subsubsection{Notification structure layout}\label{sec:Virtio Transport Options / Virtio Over PCI Bus / PCI Device Layout / Notification capability} @@ -956,9 +971,23 @@ \subsubsection{PCI configuration access capability}\label{sec:Virtio Transport O specified by some other Virtio Structure PCI Capability of type other than \field{VIRTIO_PCI_CAP_PCI_CFG}. +\subsubsection{Transitional MMR Interface: Legacy Memory Mapped Configuration Registers Capability} +\label{sec:Virtio Transport Options / Virtio Over PCI Bus / Virtio Structure PCI Capabilities / Transitional MMR Interface: Legacy Memory Mapped Configuration Registers Capability} + +The optional VIRTIO_PCI_CAP_LEGACY_MMR_CFG capability defines +the location of the legacy virtio configuration registers +followed by legacy device specific configuration registers in +the memory region BAR for the transitional MMR device. + +The \field{cap.offset} MUST be 4-byte aligned. +The \field{cap.offset} SHOULD be 4KBytes aligned and +\field{cap.length} SHOULD be 4KBytes. + +The transitional MMR device MUST present a legacy configuration +memory mapped registers capability using \field{virtio_pcie_ext_cap}. + \subsubsection{Legacy Interface: A Note on Feature Bits} -\label{sec:Virtio Transport Options / Virtio Over PCI Bus / -Virtio Structure PCI Capabilities / Legacy Interface: A Note on Feature Bits} +\label{sec:Virtio Transport Options / Virtio Over PCI Bus / Virtio Structure PCI Capabilities / Legacy Interface: A Note on Feature Bits} Only Feature Bits 0 to 31 are accessible through the Legacy Interface. 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