On Thu, Apr 13, 2023 at 11:14:31AM +0200, Pierre Gondois wrote:
> If there is no ACPI/DT information, it is assumed that L1 caches
> are private and L2 (and higher) caches are shared. A cache is
> 'shared' between two CPUs if it is accessible from these two
> CPUs.
> 
> Each CPU owns a representation (i.e. has a dedicated cacheinfo struct)
> of the caches it has access to. cache_leaves_are_shared() tries to
> identify whether two representations are designating the same actual
> cache.
> 
> In cache_leaves_are_shared(), if 'this_leaf' is a L2 cache (or higher)
> and 'sib_leaf' is a L1 cache, the caches are detected as shared as
> only this_leaf's cache level is checked.
> This is leads to setting sib_leaf as being shared with another CPU,
> which is incorrect as this is a L1 cache.
> 
> Check 'sib_leaf->level'. Also update the comment as the function is
> called when populating 'shared_cpu_map'.
> 
> Fixes: f16d1becf96f ("cacheinfo: Use cache identifiers to check if the caches are shared if available")

Cool, thanks for the updated commit message. Easier to twig the
rationale this way.
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

Thanks,
Conor.