From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
To: geert+renesas@glider.be, magnus.damm@gmail.com
Cc: linux-renesas-soc@vger.kernel.org,
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Subject: [PATCH v2] arm64: dts: renesas: Add IOMMU related properties into PCIe host nodes
Date: Wed, 26 Apr 2023 17:28:12 +0900 [thread overview]
Message-ID: <20230426082812.3621678-1-yoshihiro.shimoda.uh@renesas.com> (raw)
Add iommu-map and iommu-map-mask properties into PCIe host nodes.
Note that iommu-map-mask should be zero because the IPMMU assigns
one micro TLB ID only to the PCIe host.
Also change dma-ranges arguments for IOMMU. Notes that the dma-ranges
can be used if IOMMU is disabled.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
Changes from v1:
https://lore.kernel.org/all/20230421122608.3389397-1-yoshihiro.shimoda.uh@renesas.com/
- Drop iommus property.
- Add iommu-map-mask property.
- Revise the commit description.
arch/arm64/boot/dts/renesas/r8a77951.dtsi | 12 ++++++++----
arch/arm64/boot/dts/renesas/r8a77960.dtsi | 12 ++++++++----
arch/arm64/boot/dts/renesas/r8a77961.dtsi | 12 ++++++++----
arch/arm64/boot/dts/renesas/r8a77965.dtsi | 12 ++++++++----
arch/arm64/boot/dts/renesas/r8a77990.dtsi | 6 ++++--
5 files changed, 36 insertions(+), 18 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a77951.dtsi b/arch/arm64/boot/dts/renesas/r8a77951.dtsi
index 10b91e9733bf..2adec8b6c93f 100644
--- a/arch/arm64/boot/dts/renesas/r8a77951.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77951.dtsi
@@ -2778,8 +2778,8 @@ pciec0: pcie@fe000000 {
<0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
<0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
<0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
- /* Map all possible DDR as inbound ranges */
- dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>;
+ /* Map all possible DDR/IOMMU as inbound ranges */
+ dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
@@ -2790,6 +2790,8 @@ pciec0: pcie@fe000000 {
clock-names = "pcie", "pcie_bus";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 319>;
+ iommu-map = <0 &ipmmu_hc 0 0x10000>;
+ iommu-map-mask = <0>;
status = "disabled";
};
@@ -2805,8 +2807,8 @@ pciec1: pcie@ee800000 {
<0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
<0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
<0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
- /* Map all possible DDR as inbound ranges */
- dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>;
+ /* Map all possible DDR/IOMMU as inbound ranges */
+ dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
@@ -2817,6 +2819,8 @@ pciec1: pcie@ee800000 {
clock-names = "pcie", "pcie_bus";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 318>;
+ iommu-map = <0 &ipmmu_hc 1 0x10000>;
+ iommu-map-mask = <0>;
status = "disabled";
};
diff --git a/arch/arm64/boot/dts/renesas/r8a77960.dtsi b/arch/arm64/boot/dts/renesas/r8a77960.dtsi
index 3ea8572e917f..deeb8a8f2bc8 100644
--- a/arch/arm64/boot/dts/renesas/r8a77960.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77960.dtsi
@@ -2565,8 +2565,8 @@ pciec0: pcie@fe000000 {
<0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
<0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
<0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
- /* Map all possible DDR as inbound ranges */
- dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
+ /* Map all possible DDR/IOMMU as inbound ranges */
+ dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
@@ -2577,6 +2577,8 @@ pciec0: pcie@fe000000 {
clock-names = "pcie", "pcie_bus";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 319>;
+ iommu-map = <0 &ipmmu_hc 0 0x10000>;
+ iommu-map-mask = <0>;
status = "disabled";
};
@@ -2592,8 +2594,8 @@ pciec1: pcie@ee800000 {
<0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
<0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
<0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
- /* Map all possible DDR as inbound ranges */
- dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
+ /* Map all possible DDR/IOMMU as inbound ranges */
+ dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
@@ -2604,6 +2606,8 @@ pciec1: pcie@ee800000 {
clock-names = "pcie", "pcie_bus";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 318>;
+ iommu-map = <0 &ipmmu_hc 1 0x10000>;
+ iommu-map-mask = <0>;
status = "disabled";
};
diff --git a/arch/arm64/boot/dts/renesas/r8a77961.dtsi b/arch/arm64/boot/dts/renesas/r8a77961.dtsi
index d52cb0b67d80..bd84a79333f4 100644
--- a/arch/arm64/boot/dts/renesas/r8a77961.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77961.dtsi
@@ -2445,8 +2445,8 @@ pciec0: pcie@fe000000 {
<0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
<0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
<0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
- /* Map all possible DDR as inbound ranges */
- dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
+ /* Map all possible DDR/IOMMU as inbound ranges */
+ dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
@@ -2457,6 +2457,8 @@ pciec0: pcie@fe000000 {
clock-names = "pcie", "pcie_bus";
power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
resets = <&cpg 319>;
+ iommu-map = <0 &ipmmu_hc 0 0x10000>;
+ iommu-map-mask = <0>;
status = "disabled";
};
@@ -2472,8 +2474,8 @@ pciec1: pcie@ee800000 {
<0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
<0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
<0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
- /* Map all possible DDR as inbound ranges */
- dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
+ /* Map all possible DDR/IOMMU as inbound ranges */
+ dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
@@ -2484,6 +2486,8 @@ pciec1: pcie@ee800000 {
clock-names = "pcie", "pcie_bus";
power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
resets = <&cpg 318>;
+ iommu-map = <0 &ipmmu_hc 1 0x10000>;
+ iommu-map-mask = <0>;
status = "disabled";
};
diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
index 9584115c6b17..2319fcd30c47 100644
--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
@@ -2423,8 +2423,8 @@ pciec0: pcie@fe000000 {
<0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
<0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
<0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
- /* Map all possible DDR as inbound ranges */
- dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
+ /* Map all possible DDR/IOMMU as inbound ranges */
+ dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
@@ -2435,6 +2435,8 @@ pciec0: pcie@fe000000 {
clock-names = "pcie", "pcie_bus";
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 319>;
+ iommu-map = <0 &ipmmu_hc 0 0x10000>;
+ iommu-map-mask = <0>;
status = "disabled";
};
@@ -2450,8 +2452,8 @@ pciec1: pcie@ee800000 {
<0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
<0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
<0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
- /* Map all possible DDR as inbound ranges */
- dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
+ /* Map all possible DDR/IOMMU as inbound ranges */
+ dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
@@ -2462,6 +2464,8 @@ pciec1: pcie@ee800000 {
clock-names = "pcie", "pcie_bus";
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 318>;
+ iommu-map = <0 &ipmmu_hc 1 0x10000>;
+ iommu-map-mask = <0>;
status = "disabled";
};
diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
index 4529e9b57c33..61af0e1d3331 100644
--- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
@@ -1870,8 +1870,8 @@ pciec0: pcie@fe000000 {
<0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
<0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
<0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
- /* Map all possible DDR as inbound ranges */
- dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>;
+ /* Map all possible DDR/IOMMU as inbound ranges */
+ dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
@@ -1882,6 +1882,8 @@ pciec0: pcie@fe000000 {
clock-names = "pcie", "pcie_bus";
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 319>;
+ iommu-map = <0 &ipmmu_hc 0 0x10000>;
+ iommu-map-mask = <0>;
status = "disabled";
};
--
2.25.1
next reply other threads:[~2023-04-26 8:28 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-26 8:28 Yoshihiro Shimoda [this message]
2023-05-03 12:38 ` [PATCH v2] arm64: dts: renesas: Add IOMMU related properties into PCIe host nodes Geert Uytterhoeven
2023-05-04 7:40 ` Manivannan Sadhasivam
2023-05-08 12:09 ` Yoshihiro Shimoda
2023-05-08 12:02 ` Yoshihiro Shimoda
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