From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E633CC7EE25 for ; Thu, 4 May 2023 00:49:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229819AbjEDAt2 (ORCPT ); Wed, 3 May 2023 20:49:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55858 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229793AbjEDAtS (ORCPT ); Wed, 3 May 2023 20:49:18 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8D5E43C27; Wed, 3 May 2023 17:49:13 -0700 (PDT) Received: from notapiano.myfiosgateway.com (unknown [IPv6:2600:4041:5b1a:cd00:524d:e95d:1a9c:492a]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: nfraprado) by madras.collabora.co.uk (Postfix) with ESMTPSA id 6BC54660484E; Thu, 4 May 2023 01:49:10 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1683161352; bh=2CNvs29pjnQlFafHd+eKJGLMpmDNgELfBO2opQWPvJE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=CobGbuMmOI7OdDVvyKrh8Mq0kLTKVgdoaq83aiHNawwKnjY0xFpnznMuA+oikFP5m nLkiFR1rTfq864O8TYNgdInWxvERdpC+qFxfzKCQJgQJoqbcKonhvRTonTMoMdJ9XX 5zgfh2ucSrk3RIjF4wgfEcSWZxi3uCYqXZMHpF5C0cn9Ve65poUdBDRdeIbaU6pWWS tZcy170OCEFMy3IJ/CDeC815HBXW4wcERDwdh/+C5U/9K6jyZSu1YXqGPZ95sAz4+9 +gm5xz+MzOdtpjwwaapJvmHsnL4IMAxLLS2SqUFJxf8HztVJi5DXmOq07PlXJaTQ++ ohutEymD00fyw== From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= To: Daniel Lezcano Cc: kernel@collabora.com, Alexandre Mergnat , Balsam CHIHI , Chen-Yu Tsai , Alexandre Bailon , AngeloGioacchino Del Regno , =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= , Amit Kucheria , Matthias Brugger , "Rafael J. Wysocki" , Zhang Rui , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-pm@vger.kernel.org Subject: [PATCH v2 6/6] thermal/drivers/mediatek/lvts_thermal: Manage threshold between sensors Date: Wed, 3 May 2023 20:48:52 -0400 Message-Id: <20230504004852.627049-7-nfraprado@collabora.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230504004852.627049-1-nfraprado@collabora.com> References: <20230504004852.627049-1-nfraprado@collabora.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Each LVTS thermal controller can have up to four sensors, each capable of triggering its own interrupt when its measured temperature crosses the configured threshold. The threshold for each sensor is handled separately by the thermal framework, since each one is registered with its own thermal zone and trips. However, the temperature thresholds are configured on the controller, and therefore are shared between all sensors on that controller. When the temperature measured by the sensors is different enough to cause the thermal framework to configure different thresholds for each one, interrupts start triggering on sensors outside the last threshold configured. To address the issue, track the thresholds required by each sensor and only actually set the highest one in the hardware, and disable interrupts for all sensors outside the current configured range. Fixes: f5f633b18234 ("thermal/drivers/mediatek: Add the Low Voltage Thermal Sensor driver") Signed-off-by: Nícolas F. R. A. Prado --- Changes in v2: - Added this commit drivers/thermal/mediatek/lvts_thermal.c | 69 +++++++++++++++++++++++++ 1 file changed, 69 insertions(+) diff --git a/drivers/thermal/mediatek/lvts_thermal.c b/drivers/thermal/mediatek/lvts_thermal.c index 951a4cb75ef6..2f37a175b1c6 100644 --- a/drivers/thermal/mediatek/lvts_thermal.c +++ b/drivers/thermal/mediatek/lvts_thermal.c @@ -65,6 +65,11 @@ #define LVTS_CALSCALE_CONF 0x300 #define LVTS_MONINT_CONF 0x8300318C +#define LVTS_MONINT_OFFSET_SENSOR0 0xC +#define LVTS_MONINT_OFFSET_SENSOR1 0x180 +#define LVTS_MONINT_OFFSET_SENSOR2 0x3000 +#define LVTS_MONINT_OFFSET_SENSOR3 0x3000000 + #define LVTS_INT_SENSOR0 0x0009001F #define LVTS_INT_SENSOR1 0x001203E0 #define LVTS_INT_SENSOR2 0x00247C00 @@ -111,6 +116,8 @@ struct lvts_sensor { void __iomem *base; int id; int dt_id; + int low_thresh; + int high_thresh; }; struct lvts_ctrl { @@ -120,6 +127,8 @@ struct lvts_ctrl { int num_lvts_sensor; int mode; void __iomem *base; + int low_thresh; + int high_thresh; }; struct lvts_domain { @@ -291,12 +300,66 @@ static int lvts_get_temp(struct thermal_zone_device *tz, int *temp) return 0; } +static void lvts_update_irq_mask(struct lvts_ctrl *lvts_ctrl) +{ + u32 masks[] = { + LVTS_MONINT_OFFSET_SENSOR0, + LVTS_MONINT_OFFSET_SENSOR1, + LVTS_MONINT_OFFSET_SENSOR2, + LVTS_MONINT_OFFSET_SENSOR3, + }; + u32 value = 0; + int i; + + value = readl(LVTS_MONINT(lvts_ctrl->base)); + + for (i = 0; i < ARRAY_SIZE(masks); i++) { + if (lvts_ctrl->sensors[i].high_thresh == lvts_ctrl->high_thresh + && lvts_ctrl->sensors[i].low_thresh == lvts_ctrl->low_thresh) + value |= masks[i]; + else + value &= ~masks[i]; + } + + writel(value, LVTS_MONINT(lvts_ctrl->base)); +} + +static bool lvts_should_update_thresh(struct lvts_ctrl *lvts_ctrl, int high) +{ + int i; + + if (high > lvts_ctrl->high_thresh) + return true; + + for (i = 0; i < lvts_ctrl->num_lvts_sensor; i++) + if (lvts_ctrl->sensors[i].high_thresh == lvts_ctrl->high_thresh + && lvts_ctrl->sensors[i].low_thresh == lvts_ctrl->low_thresh) + return false; + + return true; +} + static int lvts_set_trips(struct thermal_zone_device *tz, int low, int high) { struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz); + struct lvts_ctrl *lvts_ctrl = container_of(lvts_sensor, struct lvts_ctrl, sensors[lvts_sensor->id]); void __iomem *base = lvts_sensor->base; u32 raw_low = lvts_temp_to_raw(low); u32 raw_high = lvts_temp_to_raw(high); + bool should_update_thresh; + + lvts_sensor->low_thresh = low; + lvts_sensor->high_thresh = high; + + should_update_thresh = lvts_should_update_thresh(lvts_ctrl, high); + if (should_update_thresh) { + lvts_ctrl->high_thresh = high; + lvts_ctrl->low_thresh = low; + } + lvts_update_irq_mask(lvts_ctrl); + + if (!should_update_thresh) + return 0; /* * Low offset temperature threshold @@ -527,6 +590,9 @@ static int lvts_sensor_init(struct device *dev, struct lvts_ctrl *lvts_ctrl, */ lvts_sensor[i].msr = lvts_ctrl_data->mode == LVTS_MSR_IMMEDIATE_MODE ? imm_regs[i] : msr_regs[i]; + + lvts_sensor[i].low_thresh = INT_MIN; + lvts_sensor[i].high_thresh = INT_MIN; }; lvts_ctrl->num_lvts_sensor = lvts_ctrl_data->num_lvts_sensor; @@ -721,6 +787,9 @@ static int lvts_ctrl_init(struct device *dev, struct lvts_domain *lvts_td, */ lvts_ctrl[i].hw_tshut_raw_temp = lvts_temp_to_raw(lvts_data->lvts_ctrl[i].hw_tshut_temp); + + lvts_ctrl[i].low_thresh = INT_MIN; + lvts_ctrl[i].high_thresh = INT_MIN; } /* -- 2.40.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8CFB3C77B7F for ; Thu, 4 May 2023 00:50:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=xc6vZVQaXTdhiNtL3gkxIuwEdPcV+2zy7OUZBXtxSk4=; b=ahybg1sOqJ4ihi 1EyypESrTuB8vM3u2ktf9NmsZMWCJNnmSvcunpkbw6bTkDWFN5oPoyyLKdTRrrf+4RlVjAJeWVb/g OGGd26+U2e61Xl8MMTwDXb6X/CO8qJHWFOmSsYAvctrj1pwdA9fxyGd4cQv2JTMsNGcKE97sPtEWu 0CeTEONwjH6IUWpc9acipf4vXGCGngpi/9r+Ig/AmJWcCD1/qqflOjPNpJX01mTkuhjE9KHlrPR2c gpkKkRuGLak/634uQ+RIAhryter602P/3Vhs46PRIuax0573L1xSSYCLmkxHB09JXNQcGCmSWSqfx AmM0MX9sBFrV9SHwwgqw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1puN9t-006Cp5-0s; Thu, 04 May 2023 00:49:21 +0000 Received: from madras.collabora.co.uk ([46.235.227.172]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1puN9l-006CiJ-0k; Thu, 04 May 2023 00:49:14 +0000 Received: from notapiano.myfiosgateway.com (unknown [IPv6:2600:4041:5b1a:cd00:524d:e95d:1a9c:492a]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: nfraprado) by madras.collabora.co.uk (Postfix) with ESMTPSA id 6BC54660484E; Thu, 4 May 2023 01:49:10 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1683161352; bh=2CNvs29pjnQlFafHd+eKJGLMpmDNgELfBO2opQWPvJE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=CobGbuMmOI7OdDVvyKrh8Mq0kLTKVgdoaq83aiHNawwKnjY0xFpnznMuA+oikFP5m nLkiFR1rTfq864O8TYNgdInWxvERdpC+qFxfzKCQJgQJoqbcKonhvRTonTMoMdJ9XX 5zgfh2ucSrk3RIjF4wgfEcSWZxi3uCYqXZMHpF5C0cn9Ve65poUdBDRdeIbaU6pWWS tZcy170OCEFMy3IJ/CDeC815HBXW4wcERDwdh/+C5U/9K6jyZSu1YXqGPZ95sAz4+9 +gm5xz+MzOdtpjwwaapJvmHsnL4IMAxLLS2SqUFJxf8HztVJi5DXmOq07PlXJaTQ++ ohutEymD00fyw== From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= To: Daniel Lezcano Cc: kernel@collabora.com, Alexandre Mergnat , Balsam CHIHI , Chen-Yu Tsai , Alexandre Bailon , AngeloGioacchino Del Regno , =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= , Amit Kucheria , Matthias Brugger , "Rafael J. Wysocki" , Zhang Rui , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-pm@vger.kernel.org Subject: [PATCH v2 6/6] thermal/drivers/mediatek/lvts_thermal: Manage threshold between sensors Date: Wed, 3 May 2023 20:48:52 -0400 Message-Id: <20230504004852.627049-7-nfraprado@collabora.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230504004852.627049-1-nfraprado@collabora.com> References: <20230504004852.627049-1-nfraprado@collabora.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230503_174913_558088_AFDA8CBD X-CRM114-Status: GOOD ( 18.65 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org RWFjaCBMVlRTIHRoZXJtYWwgY29udHJvbGxlciBjYW4gaGF2ZSB1cCB0byBmb3VyIHNlbnNvcnMs IGVhY2ggY2FwYWJsZQpvZiB0cmlnZ2VyaW5nIGl0cyBvd24gaW50ZXJydXB0IHdoZW4gaXRzIG1l YXN1cmVkIHRlbXBlcmF0dXJlIGNyb3NzZXMKdGhlIGNvbmZpZ3VyZWQgdGhyZXNob2xkLiBUaGUg dGhyZXNob2xkIGZvciBlYWNoIHNlbnNvciBpcyBoYW5kbGVkCnNlcGFyYXRlbHkgYnkgdGhlIHRo ZXJtYWwgZnJhbWV3b3JrLCBzaW5jZSBlYWNoIG9uZSBpcyByZWdpc3RlcmVkIHdpdGgKaXRzIG93 biB0aGVybWFsIHpvbmUgYW5kIHRyaXBzLiBIb3dldmVyLCB0aGUgdGVtcGVyYXR1cmUgdGhyZXNo b2xkcyBhcmUKY29uZmlndXJlZCBvbiB0aGUgY29udHJvbGxlciwgYW5kIHRoZXJlZm9yZSBhcmUg c2hhcmVkIGJldHdlZW4gYWxsCnNlbnNvcnMgb24gdGhhdCBjb250cm9sbGVyLgoKV2hlbiB0aGUg dGVtcGVyYXR1cmUgbWVhc3VyZWQgYnkgdGhlIHNlbnNvcnMgaXMgZGlmZmVyZW50IGVub3VnaCB0 bwpjYXVzZSB0aGUgdGhlcm1hbCBmcmFtZXdvcmsgdG8gY29uZmlndXJlIGRpZmZlcmVudCB0aHJl c2hvbGRzIGZvciBlYWNoCm9uZSwgaW50ZXJydXB0cyBzdGFydCB0cmlnZ2VyaW5nIG9uIHNlbnNv cnMgb3V0c2lkZSB0aGUgbGFzdCB0aHJlc2hvbGQKY29uZmlndXJlZC4KClRvIGFkZHJlc3MgdGhl IGlzc3VlLCB0cmFjayB0aGUgdGhyZXNob2xkcyByZXF1aXJlZCBieSBlYWNoIHNlbnNvciBhbmQK b25seSBhY3R1YWxseSBzZXQgdGhlIGhpZ2hlc3Qgb25lIGluIHRoZSBoYXJkd2FyZSwgYW5kIGRp c2FibGUKaW50ZXJydXB0cyBmb3IgYWxsIHNlbnNvcnMgb3V0c2lkZSB0aGUgY3VycmVudCBjb25m aWd1cmVkIHJhbmdlLgoKRml4ZXM6IGY1ZjYzM2IxODIzNCAoInRoZXJtYWwvZHJpdmVycy9tZWRp YXRlazogQWRkIHRoZSBMb3cgVm9sdGFnZSBUaGVybWFsIFNlbnNvciBkcml2ZXIiKQpTaWduZWQt b2ZmLWJ5OiBOw61jb2xhcyBGLiBSLiBBLiBQcmFkbyA8bmZyYXByYWRvQGNvbGxhYm9yYS5jb20+ CgotLS0KCkNoYW5nZXMgaW4gdjI6Ci0gQWRkZWQgdGhpcyBjb21taXQKCiBkcml2ZXJzL3RoZXJt YWwvbWVkaWF0ZWsvbHZ0c190aGVybWFsLmMgfCA2OSArKysrKysrKysrKysrKysrKysrKysrKysr CiAxIGZpbGUgY2hhbmdlZCwgNjkgaW5zZXJ0aW9ucygrKQoKZGlmZiAtLWdpdCBhL2RyaXZlcnMv dGhlcm1hbC9tZWRpYXRlay9sdnRzX3RoZXJtYWwuYyBiL2RyaXZlcnMvdGhlcm1hbC9tZWRpYXRl ay9sdnRzX3RoZXJtYWwuYwppbmRleCA5NTFhNGNiNzVlZjYuLjJmMzdhMTc1YjFjNiAxMDA2NDQK LS0tIGEvZHJpdmVycy90aGVybWFsL21lZGlhdGVrL2x2dHNfdGhlcm1hbC5jCisrKyBiL2RyaXZl cnMvdGhlcm1hbC9tZWRpYXRlay9sdnRzX3RoZXJtYWwuYwpAQCAtNjUsNiArNjUsMTEgQEAKICNk ZWZpbmUgTFZUU19DQUxTQ0FMRV9DT05GCQkJMHgzMDAKICNkZWZpbmUgTFZUU19NT05JTlRfQ09O RgkJCTB4ODMwMDMxOEMKIAorI2RlZmluZSBMVlRTX01PTklOVF9PRkZTRVRfU0VOU09SMAkJMHhD CisjZGVmaW5lIExWVFNfTU9OSU5UX09GRlNFVF9TRU5TT1IxCQkweDE4MAorI2RlZmluZSBMVlRT X01PTklOVF9PRkZTRVRfU0VOU09SMgkJMHgzMDAwCisjZGVmaW5lIExWVFNfTU9OSU5UX09GRlNF VF9TRU5TT1IzCQkweDMwMDAwMDAKKwogI2RlZmluZSBMVlRTX0lOVF9TRU5TT1IwCQkJMHgwMDA5 MDAxRgogI2RlZmluZSBMVlRTX0lOVF9TRU5TT1IxCQkJMHgwMDEyMDNFMAogI2RlZmluZSBMVlRT X0lOVF9TRU5TT1IyCQkJMHgwMDI0N0MwMApAQCAtMTExLDYgKzExNiw4IEBAIHN0cnVjdCBsdnRz X3NlbnNvciB7CiAJdm9pZCBfX2lvbWVtICpiYXNlOwogCWludCBpZDsKIAlpbnQgZHRfaWQ7CisJ aW50IGxvd190aHJlc2g7CisJaW50IGhpZ2hfdGhyZXNoOwogfTsKIAogc3RydWN0IGx2dHNfY3Ry bCB7CkBAIC0xMjAsNiArMTI3LDggQEAgc3RydWN0IGx2dHNfY3RybCB7CiAJaW50IG51bV9sdnRz X3NlbnNvcjsKIAlpbnQgbW9kZTsKIAl2b2lkIF9faW9tZW0gKmJhc2U7CisJaW50IGxvd190aHJl c2g7CisJaW50IGhpZ2hfdGhyZXNoOwogfTsKIAogc3RydWN0IGx2dHNfZG9tYWluIHsKQEAgLTI5 MSwxMiArMzAwLDY2IEBAIHN0YXRpYyBpbnQgbHZ0c19nZXRfdGVtcChzdHJ1Y3QgdGhlcm1hbF96 b25lX2RldmljZSAqdHosIGludCAqdGVtcCkKIAlyZXR1cm4gMDsKIH0KIAorc3RhdGljIHZvaWQg bHZ0c191cGRhdGVfaXJxX21hc2soc3RydWN0IGx2dHNfY3RybCAqbHZ0c19jdHJsKQoreworCXUz MiBtYXNrc1tdID0geworCQlMVlRTX01PTklOVF9PRkZTRVRfU0VOU09SMCwKKwkJTFZUU19NT05J TlRfT0ZGU0VUX1NFTlNPUjEsCisJCUxWVFNfTU9OSU5UX09GRlNFVF9TRU5TT1IyLAorCQlMVlRT X01PTklOVF9PRkZTRVRfU0VOU09SMywKKwl9OworCXUzMiB2YWx1ZSA9IDA7CisJaW50IGk7CisK Kwl2YWx1ZSA9IHJlYWRsKExWVFNfTU9OSU5UKGx2dHNfY3RybC0+YmFzZSkpOworCisJZm9yIChp ID0gMDsgaSA8IEFSUkFZX1NJWkUobWFza3MpOyBpKyspIHsKKwkJaWYgKGx2dHNfY3RybC0+c2Vu c29yc1tpXS5oaWdoX3RocmVzaCA9PSBsdnRzX2N0cmwtPmhpZ2hfdGhyZXNoCisJCSAgICAmJiBs dnRzX2N0cmwtPnNlbnNvcnNbaV0ubG93X3RocmVzaCA9PSBsdnRzX2N0cmwtPmxvd190aHJlc2gp CisJCQl2YWx1ZSB8PSBtYXNrc1tpXTsKKwkJZWxzZQorCQkJdmFsdWUgJj0gfm1hc2tzW2ldOwor CX0KKworCXdyaXRlbCh2YWx1ZSwgTFZUU19NT05JTlQobHZ0c19jdHJsLT5iYXNlKSk7Cit9CisK K3N0YXRpYyBib29sIGx2dHNfc2hvdWxkX3VwZGF0ZV90aHJlc2goc3RydWN0IGx2dHNfY3RybCAq bHZ0c19jdHJsLCBpbnQgaGlnaCkKK3sKKwlpbnQgaTsKKworCWlmIChoaWdoID4gbHZ0c19jdHJs LT5oaWdoX3RocmVzaCkKKwkJcmV0dXJuIHRydWU7CisKKwlmb3IgKGkgPSAwOyBpIDwgbHZ0c19j dHJsLT5udW1fbHZ0c19zZW5zb3I7IGkrKykKKwkJaWYgKGx2dHNfY3RybC0+c2Vuc29yc1tpXS5o aWdoX3RocmVzaCA9PSBsdnRzX2N0cmwtPmhpZ2hfdGhyZXNoCisJCSAgICAmJiBsdnRzX2N0cmwt PnNlbnNvcnNbaV0ubG93X3RocmVzaCA9PSBsdnRzX2N0cmwtPmxvd190aHJlc2gpCisJCQlyZXR1 cm4gZmFsc2U7CisKKwlyZXR1cm4gdHJ1ZTsKK30KKwogc3RhdGljIGludCBsdnRzX3NldF90cmlw cyhzdHJ1Y3QgdGhlcm1hbF96b25lX2RldmljZSAqdHosIGludCBsb3csIGludCBoaWdoKQogewog CXN0cnVjdCBsdnRzX3NlbnNvciAqbHZ0c19zZW5zb3IgPSB0aGVybWFsX3pvbmVfZGV2aWNlX3By aXYodHopOworCXN0cnVjdCBsdnRzX2N0cmwgKmx2dHNfY3RybCA9IGNvbnRhaW5lcl9vZihsdnRz X3NlbnNvciwgc3RydWN0IGx2dHNfY3RybCwgc2Vuc29yc1tsdnRzX3NlbnNvci0+aWRdKTsKIAl2 b2lkIF9faW9tZW0gKmJhc2UgPSBsdnRzX3NlbnNvci0+YmFzZTsKIAl1MzIgcmF3X2xvdyA9IGx2 dHNfdGVtcF90b19yYXcobG93KTsKIAl1MzIgcmF3X2hpZ2ggPSBsdnRzX3RlbXBfdG9fcmF3KGhp Z2gpOworCWJvb2wgc2hvdWxkX3VwZGF0ZV90aHJlc2g7CisKKwlsdnRzX3NlbnNvci0+bG93X3Ro cmVzaCA9IGxvdzsKKwlsdnRzX3NlbnNvci0+aGlnaF90aHJlc2ggPSBoaWdoOworCisJc2hvdWxk X3VwZGF0ZV90aHJlc2ggPSBsdnRzX3Nob3VsZF91cGRhdGVfdGhyZXNoKGx2dHNfY3RybCwgaGln aCk7CisJaWYgKHNob3VsZF91cGRhdGVfdGhyZXNoKSB7CisJCWx2dHNfY3RybC0+aGlnaF90aHJl c2ggPSBoaWdoOworCQlsdnRzX2N0cmwtPmxvd190aHJlc2ggPSBsb3c7CisJfQorCWx2dHNfdXBk YXRlX2lycV9tYXNrKGx2dHNfY3RybCk7CisKKwlpZiAoIXNob3VsZF91cGRhdGVfdGhyZXNoKQor CQlyZXR1cm4gMDsKIAogCS8qCiAJICogTG93IG9mZnNldCB0ZW1wZXJhdHVyZSB0aHJlc2hvbGQK QEAgLTUyNyw2ICs1OTAsOSBAQCBzdGF0aWMgaW50IGx2dHNfc2Vuc29yX2luaXQoc3RydWN0IGRl dmljZSAqZGV2LCBzdHJ1Y3QgbHZ0c19jdHJsICpsdnRzX2N0cmwsCiAJCSAqLwogCQlsdnRzX3Nl bnNvcltpXS5tc3IgPSBsdnRzX2N0cmxfZGF0YS0+bW9kZSA9PSBMVlRTX01TUl9JTU1FRElBVEVf TU9ERSA/CiAJCQlpbW1fcmVnc1tpXSA6IG1zcl9yZWdzW2ldOworCisJCWx2dHNfc2Vuc29yW2ld Lmxvd190aHJlc2ggPSBJTlRfTUlOOworCQlsdnRzX3NlbnNvcltpXS5oaWdoX3RocmVzaCA9IElO VF9NSU47CiAJfTsKIAogCWx2dHNfY3RybC0+bnVtX2x2dHNfc2Vuc29yID0gbHZ0c19jdHJsX2Rh dGEtPm51bV9sdnRzX3NlbnNvcjsKQEAgLTcyMSw2ICs3ODcsOSBAQCBzdGF0aWMgaW50IGx2dHNf Y3RybF9pbml0KHN0cnVjdCBkZXZpY2UgKmRldiwgc3RydWN0IGx2dHNfZG9tYWluICpsdnRzX3Rk LAogCQkgKi8KIAkJbHZ0c19jdHJsW2ldLmh3X3RzaHV0X3Jhd190ZW1wID0KIAkJCWx2dHNfdGVt cF90b19yYXcobHZ0c19kYXRhLT5sdnRzX2N0cmxbaV0uaHdfdHNodXRfdGVtcCk7CisKKwkJbHZ0 c19jdHJsW2ldLmxvd190aHJlc2ggPSBJTlRfTUlOOworCQlsdnRzX2N0cmxbaV0uaGlnaF90aHJl c2ggPSBJTlRfTUlOOwogCX0KIAogCS8qCi0tIAoyLjQwLjEKCgpfX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fXwpsaW51eC1hcm0ta2VybmVsIG1haWxpbmcgbGlz dApsaW51eC1hcm0ta2VybmVsQGxpc3RzLmluZnJhZGVhZC5vcmcKaHR0cDovL2xpc3RzLmluZnJh ZGVhZC5vcmcvbWFpbG1hbi9saXN0aW5mby9saW51eC1hcm0ta2VybmVsCg==