From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1EA96C77B7C for ; Fri, 12 May 2023 13:50:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241121AbjELNt6 (ORCPT ); Fri, 12 May 2023 09:49:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58522 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241325AbjELNty (ORCPT ); Fri, 12 May 2023 09:49:54 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 301EF12EA9; Fri, 12 May 2023 06:49:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1683899393; x=1715435393; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=DuNeysYSTXy/mIZofYnY1xvzASlALFjZdE92szRAONc=; b=jalO+Qu1oHnS0FfJgzVsS84HrwTnpOqII992QLCJf1te4pfzAhqA71d3 e5/JPXViiWgCfUhnR1J8CEAy42yukDc1X8TG9bMnApgnas6oN3W7KPSs5 aqKulDjLCCr9BwzuQgnKEf3Q+yOZ77FTq/igFZJIqzuGcbxg5Y70gfAXc R9TBX7K9THPlkWmm19EqasQavHFWsCmib+rQ/QgBlk4Df4PXoSNonSRZ4 r8vc+ZblUVm24cUoemNfMgv3K9olZfevenckc+Z1EJtbsCapoMLG8tn0a 3ggUMw88eYK9udVQOx7CmfL2EywPiQSKajicXRKFVDn8P307pNzHHIEY6 Q==; X-IronPort-AV: E=Sophos;i="5.99,269,1677567600"; d="asc'?scan'208";a="210975138" X-Amp-Result: UNKNOWN X-Amp-Original-Verdict: FILE UNKNOWN Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 12 May 2023 06:49:52 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Fri, 12 May 2023 06:49:50 -0700 Received: from wendy (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21 via Frontend Transport; Fri, 12 May 2023 06:49:48 -0700 Date: Fri, 12 May 2023 14:49:27 +0100 From: Conor Dooley To: Xingyu Wu CC: , , Michael Turquette , Stephen Boyd , Krzysztof Kozlowski , Philipp Zabel , Conor Dooley , Emil Renner Berthing , Rob Herring , Paul Walmsley , Palmer Dabbelt , Albert Ou , Hal Feng , William Qiu , , Subject: Re: [PATCH v4 3/7] dt-bindings: clock: jh7110-syscrg: Add PLL clock inputs Message-ID: <20230512-traffic-popsicle-5c3423b37fab@wendy> References: <20230512022036.97987-1-xingyu.wu@starfivetech.com> <20230512022036.97987-4-xingyu.wu@starfivetech.com> <20230512-uproar-external-49a9e793fbc4@wendy> <91e4fd3c-20cb-724b-c9a8-e038600aabb7@starfivetech.com> <20230512-backlit-radiated-ded0b38b4a94@wendy> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="qj/PZxe9T53Afs5A" Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --qj/PZxe9T53Afs5A Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Fri, May 12, 2023 at 05:56:16PM +0800, Xingyu Wu wrote: > On 2023/5/12 17:35, Conor Dooley wrote: > > On Fri, May 12, 2023 at 04:07:47PM +0800, Xingyu Wu wrote: > >> On 2023/5/12 14:47, Conor Dooley wrote: > >> > On Fri, May 12, 2023 at 10:20:32AM +0800, Xingyu Wu wrote: > >> >> Add PLL clock inputs from PLL clock generator. > >> >>=20 > >> >> Acked-by: Krzysztof Kozlowski > >> >> Signed-off-by: Xingyu Wu > >> >> --- > >> >> .../clock/starfive,jh7110-syscrg.yaml | 20 +++++++++++++++= ++-- > >> >> 1 file changed, 18 insertions(+), 2 deletions(-) > >> >=20 > >> > /tmp/tmp.KDlzwQM5ma/arch/riscv/boot/dts/starfive/jh7110-starfive-vis= ionfive-2-v1.3b.dtb: clock-controller@13020000: clocks: 'oneOf' conditional= failed, one must be fixed: > >> > [[19], [20], [21], [22], [23], [24], [25], [26], [27]] is too short > >> > From schema: /Documentation/devicetree/bindings/clock/starfive,jh71= 10-syscrg.yaml > >> > /tmp/tmp.KDlzwQM5ma/arch/riscv/boot/dts/starfive/jh7110-starfive-vis= ionfive-2-v1.3b.dtb: clock-controller@13020000: clock-names: 'oneOf' condit= ional failed, one must be fixed: > >> > ['osc', 'gmac1_rmii_refin', 'gmac1_rgmii_rxin', 'i2stx_bclk_ext', '= i2stx_lrck_ext', 'i2srx_bclk_ext', 'i2srx_lrck_ext', 'tdm_ext', 'mclk_ext']= is too short > >> > 'i2stx_bclk_ext' was expected > >> > 'i2stx_lrck_ext' was expected > >> > 'i2srx_bclk_ext' was expected > >> > 'i2srx_lrck_ext' was expected > >> > 'tdm_ext' was expected > >> > 'mclk_ext' was expected > >> > 'pll0_out' was expected > >> > From schema: /Documentation/devicetree/bindings/clock/starfive,jh71= 10-syscrg.yaml > >> > /tmp/tmp.KDlzwQM5ma/arch/riscv/boot/dts/starfive/jh7110-starfive-vis= ionfive-2-v1.2a.dtb: clock-controller@13020000: clocks: 'oneOf' conditional= failed, one must be fixed: > >> > [[19], [20], [21], [22], [23], [24], [25], [26], [27]] is too short > >> > From schema: Documentation/devicetree/bindings/clock/starfive,jh711= 0-syscrg.yaml > >> > /tmp/tmp.KDlzwQM5ma/arch/riscv/boot/dts/starfive/jh7110-starfive-vis= ionfive-2-v1.2a.dtb: clock-controller@13020000: clock-names: 'oneOf' condit= ional failed, one must be fixed: > >> > ['osc', 'gmac1_rmii_refin', 'gmac1_rgmii_rxin', 'i2stx_bclk_ext', '= i2stx_lrck_ext', 'i2srx_bclk_ext', 'i2srx_lrck_ext', 'tdm_ext', 'mclk_ext']= is too short > >> > 'i2stx_bclk_ext' was expected > >> > 'i2stx_lrck_ext' was expected > >> > 'i2srx_bclk_ext' was expected > >> > 'i2srx_lrck_ext' was expected > >> > 'tdm_ext' was expected > >> > 'mclk_ext' was expected > >> > 'pll0_out' was expected > >> > Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml > >> >=20 > >> > This binding change is incompatible with the existing devicetrees for > >> > the visionfive 2. > >>=20 > >> This looks like less clocks about PLL in SYSCRG node. And I add this i= n patch 7. > >=20 > > The existing devicetree is a valid, albeit limited, description of the > > hardware. > > After your changes to the clock driver in this series, but *without* the > > changes to the devicetrees, does the system still function? > > From a quick check of 4/7, it looks like it will not? >=20 > I just tested it on the board and the system still worked without the cha= nges > about devicetree. But these clocks' rate were 0 because these could not g= et > the PLL clocks from devicetree. Hmm, that sounds like an issue to me. If all of the clock rates are computed based off of parents that incorrectly report 0, are we not in for trouble? Should the fixed-factor clocks be retained as a fallback for the sake of compatibility? Emil, Stephen? --qj/PZxe9T53Afs5A Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCZF5D5wAKCRB4tDGHoIJi 0ls8AQDZMoyMjXuX37lw7BCSWsU9Gxef0TEiBYOlGG+R1S9i9gEAlqR+XYcFjG8B 9nGwVdlLV70d09Xp6IjHrhusCQ2QSA4= =fsw/ -----END PGP SIGNATURE----- --qj/PZxe9T53Afs5A-- From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CF196C77B7C for ; Fri, 12 May 2023 13:50:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type: List-Subscribe:List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id: In-Reply-To:MIME-Version:References:Message-ID:Subject:CC:To:From:Date: Reply-To:Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date :Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=1Lr4YfohO5tVxnUKmkQjOt7/p1jxWnEEABshzLJmF24=; b=TXBnaDLMb7kDPNXgaMgS1SqhHj u6AiPb/j8kEaYlbF4ljREvJHyvUmhLQfplVRWg/hIm0WISKj1sj4848NsLg7mxJ5HFe7ZAonfDWIP yqMIP87f3L8USXVrCqJKFbvozNi9CXai5gOWPTlCoYzaczBiw8JsaQMKVsJHQZst40fvrz9pzf2lJ KW19k8V6HM0We7LRmikICcwUylTSZvk52JQ3fj0G1RUP6wm+2go1mqrZBoP277uz0U0EgqqEtJdZI 8/6rfVHn0AENAVng1fnOGHiCZx/Gw0zNyT2Fw8PyrVh/UI0DHDsXwRLdiIHHzkuioj6UT9MF1SdHF Sx5SRX4A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1pxT9k-00C49l-1E; Fri, 12 May 2023 13:50:00 +0000 Received: from esa.microchip.iphmx.com ([68.232.154.123]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1pxT9g-00C48x-2e for linux-riscv@lists.infradead.org; Fri, 12 May 2023 13:49:59 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1683899397; x=1715435397; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=DuNeysYSTXy/mIZofYnY1xvzASlALFjZdE92szRAONc=; b=vWP2EEnXK0qQwZQ5j8AThylijIdjtUSjomYDX23RaKrwEuXad6lEDf5U 1iEtmCk+eSuv0LzJw2k3HJXqBdsB0onQ4/3wiJTTpmPPMedB2AkMpXFFA 1i+GO3GOtROFL3uZR/rZsxE9afIYfWVyu+zSF9P1Vp9yZauwwzr4Zi1jj E3Brrpzr6Ti/jh75EQ0HspWIjogmz7SRHyaC61Wo6QErXAxvUXTnoa7Rs 71hiQLF+pAnDdzdaBcjXuObvIJq0TxpyN0dJ8DNFY2Eppb8n1ZaP3HEvf J+oWI0g89un9DQ4H+uue9poWvIb9/V04RTjAq3qsRkJJ7JwR6IkWHn9ek Q==; X-IronPort-AV: E=Sophos;i="5.99,269,1677567600"; d="asc'?scan'208";a="210975138" X-Amp-Result: UNKNOWN X-Amp-Original-Verdict: FILE UNKNOWN Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 12 May 2023 06:49:52 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Fri, 12 May 2023 06:49:50 -0700 Received: from wendy (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21 via Frontend Transport; Fri, 12 May 2023 06:49:48 -0700 Date: Fri, 12 May 2023 14:49:27 +0100 From: Conor Dooley To: Xingyu Wu CC: , , Michael Turquette , Stephen Boyd , Krzysztof Kozlowski , Philipp Zabel , Conor Dooley , Emil Renner Berthing , Rob Herring , Paul Walmsley , Palmer Dabbelt , Albert Ou , Hal Feng , William Qiu , , Subject: Re: [PATCH v4 3/7] dt-bindings: clock: jh7110-syscrg: Add PLL clock inputs Message-ID: <20230512-traffic-popsicle-5c3423b37fab@wendy> References: <20230512022036.97987-1-xingyu.wu@starfivetech.com> <20230512022036.97987-4-xingyu.wu@starfivetech.com> <20230512-uproar-external-49a9e793fbc4@wendy> <91e4fd3c-20cb-724b-c9a8-e038600aabb7@starfivetech.com> <20230512-backlit-radiated-ded0b38b4a94@wendy> MIME-Version: 1.0 In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230512_064957_053521_33F2200B X-CRM114-Status: GOOD ( 21.76 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: multipart/mixed; boundary="===============7357336362263696100==" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org --===============7357336362263696100== Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="qj/PZxe9T53Afs5A" Content-Disposition: inline --qj/PZxe9T53Afs5A Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Fri, May 12, 2023 at 05:56:16PM +0800, Xingyu Wu wrote: > On 2023/5/12 17:35, Conor Dooley wrote: > > On Fri, May 12, 2023 at 04:07:47PM +0800, Xingyu Wu wrote: > >> On 2023/5/12 14:47, Conor Dooley wrote: > >> > On Fri, May 12, 2023 at 10:20:32AM +0800, Xingyu Wu wrote: > >> >> Add PLL clock inputs from PLL clock generator. > >> >>=20 > >> >> Acked-by: Krzysztof Kozlowski > >> >> Signed-off-by: Xingyu Wu > >> >> --- > >> >> .../clock/starfive,jh7110-syscrg.yaml | 20 +++++++++++++++= ++-- > >> >> 1 file changed, 18 insertions(+), 2 deletions(-) > >> >=20 > >> > /tmp/tmp.KDlzwQM5ma/arch/riscv/boot/dts/starfive/jh7110-starfive-vis= ionfive-2-v1.3b.dtb: clock-controller@13020000: clocks: 'oneOf' conditional= failed, one must be fixed: > >> > [[19], [20], [21], [22], [23], [24], [25], [26], [27]] is too short > >> > From schema: /Documentation/devicetree/bindings/clock/starfive,jh71= 10-syscrg.yaml > >> > /tmp/tmp.KDlzwQM5ma/arch/riscv/boot/dts/starfive/jh7110-starfive-vis= ionfive-2-v1.3b.dtb: clock-controller@13020000: clock-names: 'oneOf' condit= ional failed, one must be fixed: > >> > ['osc', 'gmac1_rmii_refin', 'gmac1_rgmii_rxin', 'i2stx_bclk_ext', '= i2stx_lrck_ext', 'i2srx_bclk_ext', 'i2srx_lrck_ext', 'tdm_ext', 'mclk_ext']= is too short > >> > 'i2stx_bclk_ext' was expected > >> > 'i2stx_lrck_ext' was expected > >> > 'i2srx_bclk_ext' was expected > >> > 'i2srx_lrck_ext' was expected > >> > 'tdm_ext' was expected > >> > 'mclk_ext' was expected > >> > 'pll0_out' was expected > >> > From schema: /Documentation/devicetree/bindings/clock/starfive,jh71= 10-syscrg.yaml > >> > /tmp/tmp.KDlzwQM5ma/arch/riscv/boot/dts/starfive/jh7110-starfive-vis= ionfive-2-v1.2a.dtb: clock-controller@13020000: clocks: 'oneOf' conditional= failed, one must be fixed: > >> > [[19], [20], [21], [22], [23], [24], [25], [26], [27]] is too short > >> > From schema: Documentation/devicetree/bindings/clock/starfive,jh711= 0-syscrg.yaml > >> > /tmp/tmp.KDlzwQM5ma/arch/riscv/boot/dts/starfive/jh7110-starfive-vis= ionfive-2-v1.2a.dtb: clock-controller@13020000: clock-names: 'oneOf' condit= ional failed, one must be fixed: > >> > ['osc', 'gmac1_rmii_refin', 'gmac1_rgmii_rxin', 'i2stx_bclk_ext', '= i2stx_lrck_ext', 'i2srx_bclk_ext', 'i2srx_lrck_ext', 'tdm_ext', 'mclk_ext']= is too short > >> > 'i2stx_bclk_ext' was expected > >> > 'i2stx_lrck_ext' was expected > >> > 'i2srx_bclk_ext' was expected > >> > 'i2srx_lrck_ext' was expected > >> > 'tdm_ext' was expected > >> > 'mclk_ext' was expected > >> > 'pll0_out' was expected > >> > Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml > >> >=20 > >> > This binding change is incompatible with the existing devicetrees for > >> > the visionfive 2. > >>=20 > >> This looks like less clocks about PLL in SYSCRG node. And I add this i= n patch 7. > >=20 > > The existing devicetree is a valid, albeit limited, description of the > > hardware. > > After your changes to the clock driver in this series, but *without* the > > changes to the devicetrees, does the system still function? > > From a quick check of 4/7, it looks like it will not? >=20 > I just tested it on the board and the system still worked without the cha= nges > about devicetree. But these clocks' rate were 0 because these could not g= et > the PLL clocks from devicetree. Hmm, that sounds like an issue to me. If all of the clock rates are computed based off of parents that incorrectly report 0, are we not in for trouble? Should the fixed-factor clocks be retained as a fallback for the sake of compatibility? Emil, Stephen? --qj/PZxe9T53Afs5A Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCZF5D5wAKCRB4tDGHoIJi 0ls8AQDZMoyMjXuX37lw7BCSWsU9Gxef0TEiBYOlGG+R1S9i9gEAlqR+XYcFjG8B 9nGwVdlLV70d09Xp6IjHrhusCQ2QSA4= =fsw/ -----END PGP SIGNATURE----- --qj/PZxe9T53Afs5A-- --===============7357336362263696100== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv --===============7357336362263696100==--