All of lore.kernel.org
 help / color / mirror / Atom feed
From: Andre Przywara <andre.przywara@arm.com>
To: Sam Edwards <cfsworks@gmail.com>
Cc: Samuel Holland <samuel@sholland.org>,
	Jagan Teki <jagan@amarulasolutions.com>,
	u-boot@lists.denx.de, Icenowy Zheng <uwu@icenowy.me>,
	Jernej Skrabec <jernej.skrabec@gmail.com>
Subject: Re: [RFC PATCH 13/17] sunxi: add early Allwinner R528/T113 SoC support
Date: Tue, 16 May 2023 23:01:15 +0100	[thread overview]
Message-ID: <20230516230115.670dc94a@slackpad.lan> (raw)
In-Reply-To: <ecdb1cf3-6b86-74dc-7e49-9778c97455c5@gmail.com>

On Mon, 15 May 2023 20:52:23 -0600
Sam Edwards <cfsworks@gmail.com> wrote:

Hi Sam,

> On 12/5/22 17:45, Andre Przywara wrote:
> > diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
> > index 3763ec3d2e4..33331cda5e2 100644
> > --- a/arch/arm/mach-sunxi/board.c
> > +++ b/arch/arm/mach-sunxi/board.c
> > @@ -148,6 +148,10 @@ static int gpio_init(void)
> >   	sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0);
> >   	sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0);
> >   	sunxi_gpio_set_pull(SUNXI_GPH(13), SUNXI_GPIO_PULL_UP);
> > +#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_R528)
> > +	sunxi_gpio_set_cfgpin(SUNXI_GPE(2), 6);
> > +	sunxi_gpio_set_cfgpin(SUNXI_GPE(3), 6);
> > +	sunxi_gpio_set_pull(SUNXI_GPE(3), SUNXI_GPIO_PULL_UP);
> >   #elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUNIV)
> >   	sunxi_gpio_set_cfgpin(SUNXI_GPA(2), SUNIV_GPE_UART0);
> >   	sunxi_gpio_set_cfgpin(SUNXI_GPA(3), SUNIV_GPE_UART0);  
> 
> I'm a relative outsider to sunxi, but it does look like the NCAT2 
> generation's MUX is a lot more flexible in its UART assignments: e.g. 
> while H3's UART1-3 only had one set of pins each UART could use, the 
> T113 (my target) supports anywhere from 2-6 (typically 4) different 
> options for each of its UARTs. It is not as simple as configuring which 
> UART is the serial console anymore, because different boards might wire 
> the console header to different pins. My particular target uses UART3 on 
> pins PB6/PB7, for example.

Well, theoretically there are indeed quite some options, but in reality
we find that most boards follow some reference design, and the *debug*
UART is only ever using a very few of the possible settings. For the
later (ARMv8) SoCs this is mostly UART0, but for the T113 it's
apparently indeed UART3. I also changed that in the Github version, to
use the very same PB6/7 UART3 mux as you.

> Since this patchset is updating the PIO driver anyway, maybe it's worth 
> updating the (preprocessor, not runtime) logic in gpio_init to support 
> getting the UART TX/RX pins from Kconfig, validating that the 
> CONFIG_CONS_INDEX and pin selection are compatible, and setting the 
> correct MUX function for those pins with a value pulled from a table?

Mmmh, that's an idea one could follow, as this function is indeed
insane. I actually rewrote gpio_init() already, to replace the hard to
read #ifdef's with actual C if statements, though that's still
following the same idea as the current code.
Let me have a look how this would look like.

Cheers,
Andre

  reply	other threads:[~2023-05-16 22:01 UTC|newest]

Thread overview: 62+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-12-06  0:45 [RFC PATCH 00/17] sunxi: rework pinctrl and add T113s support Andre Przywara
2022-12-06  0:45 ` [RFC PATCH 01/17] sunxi: remove CONFIG_SATAPWR Andre Przywara
2022-12-14  8:37   ` Samuel Holland
2022-12-14 14:25     ` Andre Przywara
2022-12-14 23:40       ` Samuel Holland
2022-12-06  0:45 ` [RFC PATCH 02/17] sunxi: remove CONFIG_MACPWR Andre Przywara
2022-12-14  9:09   ` Samuel Holland
2022-12-14 14:23     ` Andre Przywara
2022-12-06  0:45 ` [RFC PATCH 03/17] pinctrl: sunxi: remove struct sunxi_gpio Andre Przywara
2022-12-06  0:45 ` [RFC PATCH 04/17] pinctrl: sunxi: add GPIO in/out wrappers Andre Przywara
2022-12-15  5:59   ` Samuel Holland
2022-12-06  0:45 ` [RFC PATCH 05/17] pinctrl: sunxi: move pinctrl code and remove GPIO_EXTRA_HEADER Andre Przywara
2022-12-06  0:45 ` [RFC PATCH 06/17] pinctrl: sunxi: move PIO_BASE into sunxi_gpio.h Andre Przywara
2022-12-06  0:45 ` [RFC PATCH 07/17] pinctrl: sunxi: add new D1 pinctrl support Andre Przywara
2022-12-06  0:45 ` [RFC PATCH 08/17] sunxi: introduce NCAT2 generation model Andre Przywara
2022-12-06  5:38   ` Icenowy Zheng
2023-05-16  2:32   ` Sam Edwards
2023-05-16 21:08     ` Andre Przywara
2023-05-16 23:53       ` Sam Edwards
2023-05-17  0:43         ` Andre Przywara
2023-05-17  8:56           ` Andre Przywara
2023-05-17 14:04             ` Maxim Kiselev
2023-05-25 18:25               ` Maksim Kiselev
2023-05-26 11:05                 ` Andre Przywara
2023-06-03 18:03   ` Sam Edwards
2022-12-06  0:45 ` [RFC PATCH 09/17] pinctrl: sunxi: add Allwinner D1 pinctrl description Andre Przywara
2022-12-06  0:45 ` [RFC PATCH 10/17] clk: sunxi: Add support for the D1 CCU Andre Przywara
2023-05-22  3:57   ` Sam Edwards
2023-05-24  0:58     ` Andre Przywara
2023-05-26  0:34   ` Sam Edwards
2023-05-26 10:50     ` Andre Przywara
2023-05-26 19:27       ` Maksim Kiselev
2023-05-26 20:22         ` Sam Edwards
2023-05-26 22:07           ` Andre Przywara
2023-05-27  2:15             ` Sam Edwards
2023-05-30  0:58               ` Sam Edwards
2023-05-31 15:19                 ` Andre Przywara
2022-12-06  0:45 ` [RFC PATCH 11/17] sunxi: clock: D1/R528: Enable PLL LDO during PLL1 setup Andre Przywara
2022-12-06  0:45 ` [RFC PATCH 12/17] sunxi: clock: support D1/R528 PLL6 clock Andre Przywara
2022-12-06  0:45 ` [RFC PATCH 13/17] sunxi: add early Allwinner R528/T113 SoC support Andre Przywara
2023-05-16  2:52   ` Sam Edwards
2023-05-16 22:01     ` Andre Przywara [this message]
2022-12-06  0:45 ` [RFC PATCH 14/17] sunxi: refactor serial base addresses to avoid asm/arch/cpu.h Andre Przywara
2022-12-06  0:45 ` [RFC PATCH 15/17] riscv: dts: allwinner: Add the D1/D1s SoC devicetree Andre Przywara
2022-12-06  0:45 ` [RFC PATCH 16/17] arm: sunxi: add Allwinner T113s devicetree stub Andre Przywara
2022-12-06  5:55   ` Icenowy Zheng
2023-01-03 17:38     ` Andre Przywara
2023-01-04  5:49       ` Icenowy Zheng
2022-12-06  0:45 ` [RFC PATCH 17/17] sunxi: add preliminary MangoPi MQ-R board support Andre Przywara
2023-06-09 22:16 ` [RFC PATCH 00/17] sunxi: rework pinctrl and add T113s support Sam Edwards
2023-06-12  0:20   ` Andre Przywara
2023-06-12 21:18     ` Sam Edwards
2023-06-15  0:07       ` Andre Przywara
2023-06-18 19:01         ` Sam Edwards
2023-06-20 12:42           ` Andre Przywara
2023-06-20 22:11             ` Sam Edwards
2023-06-21 10:55               ` Andre Przywara
2023-06-21 20:22                 ` Sam Edwards
2023-06-16 15:59       ` Andre Przywara
2023-06-16 16:27         ` Maxim Kiselev
2023-06-16 16:36           ` Andre Przywara
2023-06-17  8:26             ` Maxim Kiselev

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20230516230115.670dc94a@slackpad.lan \
    --to=andre.przywara@arm.com \
    --cc=cfsworks@gmail.com \
    --cc=jagan@amarulasolutions.com \
    --cc=jernej.skrabec@gmail.com \
    --cc=samuel@sholland.org \
    --cc=u-boot@lists.denx.de \
    --cc=uwu@icenowy.me \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.