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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 02/21] hw/arm/smmuv3: Add missing fields for IDR0
Date: Tue, 30 May 2023 14:26:01 +0100	[thread overview]
Message-ID: <20230530132620.1583658-3-peter.maydell@linaro.org> (raw)
In-Reply-To: <20230530132620.1583658-1-peter.maydell@linaro.org>

From: Mostafa Saleh <smostafa@google.com>

In preparation for adding stage-2 support.
Add IDR0 fields related to stage-2.

VMID16: 16-bit VMID supported.
S2P: Stage-2 translation supported.

They are described in 6.3.1 SMMU_IDR0.

No functional change intended.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Mostafa Saleh <smostafa@google.com>
Tested-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Message-id: 20230516203327.2051088-2-smostafa@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/smmuv3-internal.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h
index e8f0ebf25e3..183d5ac8dca 100644
--- a/hw/arm/smmuv3-internal.h
+++ b/hw/arm/smmuv3-internal.h
@@ -34,10 +34,12 @@ typedef enum SMMUTranslationStatus {
 /* MMIO Registers */
 
 REG32(IDR0,                0x0)
+    FIELD(IDR0, S2P,         0 , 1)
     FIELD(IDR0, S1P,         1 , 1)
     FIELD(IDR0, TTF,         2 , 2)
     FIELD(IDR0, COHACC,      4 , 1)
     FIELD(IDR0, ASID16,      12, 1)
+    FIELD(IDR0, VMID16,      18, 1)
     FIELD(IDR0, TTENDIAN,    21, 2)
     FIELD(IDR0, STALL_MODEL, 24, 2)
     FIELD(IDR0, TERM_MODEL,  26, 1)
-- 
2.34.1



  parent reply	other threads:[~2023-05-30 13:30 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-05-30 13:25 [PULL 00/21] target-arm queue Peter Maydell
2023-05-30 13:26 ` [PULL 01/21] fsl-imx6: Add SNVS support for i.MX6 boards Peter Maydell
2023-05-30 13:26 ` Peter Maydell [this message]
2023-05-30 13:26 ` [PULL 03/21] hw/arm/smmuv3: Update translation config to hold stage-2 Peter Maydell
2023-05-30 13:26 ` [PULL 04/21] hw/arm/smmuv3: Refactor stage-1 PTW Peter Maydell
2023-05-30 13:26 ` [PULL 05/21] hw/arm/smmuv3: Add page table walk for stage-2 Peter Maydell
2023-05-30 13:26 ` [PULL 06/21] hw/arm/smmuv3: Parse STE config " Peter Maydell
2023-05-30 13:26 ` [PULL 07/21] hw/arm/smmuv3: Make TLB lookup work " Peter Maydell
2023-05-30 13:26 ` [PULL 08/21] hw/arm/smmuv3: Add VMID to TLB tagging Peter Maydell
2023-05-30 13:26 ` [PULL 09/21] hw/arm/smmuv3: Add CMDs related to stage-2 Peter Maydell
2023-05-30 13:26 ` [PULL 10/21] hw/arm/smmuv3: Add stage-2 support in iova notifier Peter Maydell
2023-05-30 13:26 ` [PULL 11/21] hw/arm/smmuv3: Add knob to choose translation stage and enable stage-2 Peter Maydell
2023-05-30 13:26 ` [PULL 12/21] hw/dma/xilinx_axidma: Check DMASR.HALTED to prevent infinite loop Peter Maydell
2023-05-30 13:26 ` [PULL 13/21] hw/arm/xlnx-zynqmp: fix unsigned error when checking the RPUs number Peter Maydell
2023-05-30 13:26 ` [PULL 14/21] tests/qtest: Run arm-specific tests only if the required machine is available Peter Maydell
2023-05-30 13:26 ` [PULL 15/21] target/arm: Explicitly select short-format FSR for M-profile Peter Maydell
2023-05-30 13:26 ` [PULL 16/21] target/arm: Explain why we need to select ARM_V7M Peter Maydell
2023-05-30 13:26 ` [PULL 17/21] arm/Kconfig: Keep Kconfig default entries in default.mak as documentation Peter Maydell
2023-05-30 13:26 ` [PULL 18/21] arm/Kconfig: Make TCG dependence explicit Peter Maydell
2023-05-30 13:26 ` [PULL 19/21] Update copyright dates to 2023 Peter Maydell
2023-05-30 13:26 ` [PULL 20/21] hw/arm/sbsa-ref: add GIC node into DT Peter Maydell
2023-05-30 13:26 ` [PULL 21/21] docs: sbsa: correct graphics card name Peter Maydell
2023-05-30 14:13 ` [PULL 00/21] target-arm queue Richard Henderson

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