From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F27B0C7EE23 for ; Wed, 31 May 2023 15:19:47 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 24DFC861C0; Wed, 31 May 2023 17:19:46 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id CAD4E861FC; Wed, 31 May 2023 17:19:43 +0200 (CEST) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by phobos.denx.de (Postfix) with ESMTP id 5205F8600A for ; Wed, 31 May 2023 17:19:41 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=andre.przywara@arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id DEB2F1042; Wed, 31 May 2023 08:20:25 -0700 (PDT) Received: from donnerap.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1A8283F663; Wed, 31 May 2023 08:19:39 -0700 (PDT) Date: Wed, 31 May 2023 16:19:37 +0100 From: Andre Przywara To: Sam Edwards Cc: Maksim Kiselev , u-boot@lists.denx.de Subject: Re: [RFC PATCH 10/17] clk: sunxi: Add support for the D1 CCU Message-ID: <20230531161937.20d37f54@donnerap.cambridge.arm.com> In-Reply-To: <0eba5e2e-b1f2-dd3d-c025-c96c84375b1f@gmail.com> References: <20221206004549.29015-1-andre.przywara@arm.com> <20221206004549.29015-11-andre.przywara@arm.com> <9d95e7f4-4ec2-b025-df11-22e2101b1fc9@gmail.com> <20230526115015.33d1cea3@slackpad.lan> <2e81c57f-549a-c655-65cb-bd6bd6b72902@gmail.com> <4d85a769-7a03-dfba-6069-344aed26e889@gmail.com> <20230526230755.2157235e@slackpad.lan> <0eba5e2e-b1f2-dd3d-c025-c96c84375b1f@gmail.com> Organization: ARM X-Mailer: Claws Mail 3.18.0 (GTK+ 2.24.32; aarch64-unknown-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean On Mon, 29 May 2023 18:58:54 -0600 Sam Edwards wrote: Hi Sam, > On 5/26/23 20:15, Sam Edwards wrote: > > My "no success" is Linux stalling indefinitely at: > > [=C2=A0=C2=A0=C2=A0 0.123090] smp: Bringing up secondary CPUs ... =20 >=20 > OK, correction: my "no success" was Linux being unable to access the=20 > GIC, so boot was getting stuck. This was because it was running in=20 > nonsec mode and the GIC wasn't getting the interrupts moved over into=20 > group1. >=20 > The root cause of THAT was that the T113's CBAR's PERIPHBASE is still=20 > 0x01C80000, where the GIC used to be on the older ARM sunxis. Allwinner=20 > never updated their ARM cores when they moved the GIC to 0x03020000! Ah, good find! And yeah, I already noticed that on the H6 a few years back, but nobody really cares, and other SoCs get CBAR wrong as well (hence the existing workaround). > Guess we need a `#define CFG_ARM_GIC_BASE_ADDRESS 0x03020000`. Where do=20 > you recommend I put that? :) Meh, the reflex would be to put it in include/configs/sunxi-common.h. Although I wonder if it really belongs into Kconfig, but that may be for another time. > I also think sunxi/psci.c:psci_arch_init needs some cleanup: > - It sets GICC_PMR to 0xFF, which should probably be removed because=20 > that was already done by `_nonsec_init` > - It tries to clear the NS bit of SCR to enter secure mode, but the NS=20 > bit is just enabled later in `_secure_monitor`. So that should also be=20 > removed because it has no effect. >=20 > So, I'll have a few PSCI patches for you soon -- once I rest up from all= =20 > of that GIC debugging, that is! Ah, sorry to hear that, the GIC can really be a beast ;-) Cheers, Andre