From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CAAFCC77B7E for ; Thu, 1 Jun 2023 10:01:51 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id AA190862DA; Thu, 1 Jun 2023 12:01:00 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=denx.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1685613661; bh=3j6m/8L5c25qaQ0/JW/kMgWj1u1J0dhwfXdcdMmiR9g=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=lYtpxZMNnFmRsApEk/ohqvaIDkeX2Rr3PHzxBozrHK2jkq8a+5ktEWQ3/QvcdE4o0 9oZbOCKw2VRk2dx6CIhklA8PpQifHkbf8+4OOKphCN+0e0z3VQ8XBBP6Lhe+lSq+Kk 3HfUlogUX+6req2to/rztXUXtL8EWkMhOrFwcosX0x0iWU2kimRkq6lKv9XKXdcl3X ZrPI86P8wkA1oggMjPXGSV4O3NG2GuR0WWBpN08eQK6UFiyyec0ta6Qch0sAtvrtsz scCw9YGd2DPPFvQV0fMNwdhIwRV6JeM1/r0fsueXnQgSo4Y6hvn4swJHbS3i0McgPL VXFgdJ99oPWFA== Received: from localhost.localdomain (85-222-111-42.dynamic.chello.pl [85.222.111.42]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: lukma@denx.de) by phobos.denx.de (Postfix) with ESMTPSA id 204D3862DA; Thu, 1 Jun 2023 12:00:32 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1685613632; bh=3j6m/8L5c25qaQ0/JW/kMgWj1u1J0dhwfXdcdMmiR9g=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=MmcScieRbvM+qtjbXIgJEvSWSb5qfbbriAYD3ldWI653xl/WddIF/irzgYT6ndU/E jOCy+MNf8fmKuGSsbR2Q0JEoynj5rXxxNaT5qt0NxuqjrY0aOAQEB5OyRHZkyV0HGX rmkyLfELLq3gKKbERpfZ8J0qZ0C3hSM7JDBUVuKiTiZrmf7mncIfc9C3ZtuiDjJVx7 9I9/gGi2Mir83fQicVnfG814FvVc3+D1FkEcc3Pbzq7PPTLU8NsFsuHciX11ontQKE 3Us0gdMnlLJfqN65kFkAI/RefHEACIF+7vQOmiiwJ6xo2bM513UmK7gnU475MW8P7w OcAiAHTk/wNOw== From: Lukasz Majewski To: u-boot@lists.denx.de, Tom Rini Cc: Anatolij Gustschin , Lukasz Majewski , Ramon Fried , Joe Hershberger , Marek Vasut , Michal Simek Subject: [PATCH v1 5/6] net: mv88e61xx: Set proper offset when R0_LED/ADDR4 is set on bootstrap Date: Thu, 1 Jun 2023 12:00:04 +0200 Message-Id: <20230601100005.2216345-6-lukma@denx.de> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230601100005.2216345-1-lukma@denx.de> References: <20230601100005.2216345-1-lukma@denx.de> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean The mv88e61xx driver need to be adjusted to handle situation when switch MDIO addresses are switched by offset (0x10 in this case). Signed-off-by: Lukasz Majewski Reviewed-by: Ramon Fried --- drivers/net/phy/mv88e61xx.c | 25 ++++++++++++++++++------- 1 file changed, 18 insertions(+), 7 deletions(-) diff --git a/drivers/net/phy/mv88e61xx.c b/drivers/net/phy/mv88e61xx.c index c9917953f3d7..69a87bead469 100644 --- a/drivers/net/phy/mv88e61xx.c +++ b/drivers/net/phy/mv88e61xx.c @@ -45,7 +45,6 @@ #define PORT_MASK(port_count) ((1 << (port_count)) - 1) /* Device addresses */ -#define DEVADDR_PHY(p) (p) #define DEVADDR_SERDES 0x0F /* SMI indirection registers for multichip addressing mode */ @@ -406,7 +405,7 @@ static int mv88e61xx_phy_write_indirect(struct mii_dev *smi_wrapper, int dev, /* Wrapper function to make calls to phy_read_indirect simpler */ static int mv88e61xx_phy_read(struct phy_device *phydev, int phy, int reg) { - return mv88e61xx_phy_read_indirect(phydev->bus, DEVADDR_PHY(phy), + return mv88e61xx_phy_read_indirect(phydev->bus, phydev->addr, MDIO_DEVAD_NONE, reg); } @@ -414,7 +413,7 @@ static int mv88e61xx_phy_read(struct phy_device *phydev, int phy, int reg) static int mv88e61xx_phy_write(struct phy_device *phydev, int phy, int reg, u16 val) { - return mv88e61xx_phy_write_indirect(phydev->bus, DEVADDR_PHY(phy), + return mv88e61xx_phy_write_indirect(phydev->bus, phydev->addr, MDIO_DEVAD_NONE, reg, val); } @@ -918,12 +917,21 @@ static int mv88e61xx_priv_reg_offs_pre_init(struct phy_device *phydev) /* * Now try via port registers with device address 0x08 * (88E6020 and compatible switches). + * + * When R0_LED/ADDR4 is set during bootstrap, one needs + * to add 0x10 offset to switch addresses. + * + * The phydev->addr is set according to device tree address + * of MDIO accessible device: + * + * When on board RO_LED/ADDR4 = 1 -> 0x10 + * 0 -> 0x0 */ - priv->port_reg_base = 0x08; + priv->port_reg_base = 0x08 + phydev->addr; priv->id = mv88e61xx_get_switch_id(phydev); if (priv->id != 0xfff0) { - priv->global1 = 0x0F; - priv->global2 = 0x07; + priv->global1 = 0x0F + phydev->addr; + priv->global2 = 0x07 + phydev->addr; return 0; } @@ -1082,7 +1090,10 @@ static int mv88e61xx_phy_config(struct phy_device *phydev) for (i = 0; i < priv->port_count; i++) { if ((1 << i) & CONFIG_MV88E61XX_PHY_PORTS) { - phydev->addr = i; + if (phydev->addr) + phydev->addr += i; + else + phydev->addr = i; res = mv88e61xx_phy_enable(phydev, i); if (res < 0) { -- 2.30.2