From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 94D59C7EE2A for ; Fri, 2 Jun 2023 07:08:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234023AbjFBHI1 (ORCPT ); Fri, 2 Jun 2023 03:08:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59908 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233828AbjFBHIX (ORCPT ); Fri, 2 Jun 2023 03:08:23 -0400 Received: from muru.com (muru.com [72.249.23.125]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 441961A1; Fri, 2 Jun 2023 00:08:19 -0700 (PDT) Received: from localhost (localhost [127.0.0.1]) by muru.com (Postfix) with ESMTPS id B9DAD8111; Fri, 2 Jun 2023 07:08:18 +0000 (UTC) Date: Fri, 2 Jun 2023 10:08:17 +0300 From: Tony Lindgren To: Nishanth Menon Cc: Conor Dooley , Krzysztof Kozlowski , Rob Herring , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Tero Kristo , Vignesh Raghavendra , Udit Kumar , Nitin Yadav , Neha Malcom Francis Subject: Re: [PATCH 2/6] arm64: dts: ti: k3-j721e: Configure pinctrl for timer IO Message-ID: <20230602070817.GI14287@atomide.com> References: <20230531213215.602395-1-nm@ti.com> <20230531213215.602395-3-nm@ti.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230531213215.602395-3-nm@ti.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org * Nishanth Menon [230531 21:32]: > There are timer IO pads in the MCU domain, and in the MAIN domain. These > pads can be muxed for the related timers. > > There are timer IO control registers for input and output. The registers > for CTRLMMR_TIMER*_CTRL and CTRLMMR_MCU_TIMER*_CTRL are used to control > the input. The registers for CTCTRLMMR_TIMERIO*_CTRL and > CTRLMMR_MCU_TIMERIO*_CTRL the output. > > The multiplexing is documented in Technical Reference Manual[1] under > "Timer IO Muxing Control Registers" and "Timer IO Muxing Control > Registers", and the "Timers Overview" chapters. > > We do not expose the cascade_en bit due to the racy usage of > independent 32 bit registers in-line with the timer instantiation in > the device tree. The MCU timer controls are also marked as reserved for > usage by the MCU firmware. Reviewed-by: Tony Lindgren From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 54C3DC7EE24 for ; Fri, 2 Jun 2023 07:08:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=MxHpEUWzZK+YzAtJ0DNrKfzoc6aL43HFx9+xtIEl9Lc=; b=kxzR73VKFUhB6K RZrU44RhTSq8FZJ/2Gdc5mZgpYry7sgGL7dXCJIL9yv1VcZ0/yJ6H+qmVJPm6H5blXc0yikPwDrS6 LlA85SpcL/l33QcmCDcsjLyLpSExS2EGXaPZRj/v4J1tpgH8CPBVeQpvyPA4y7q9MjFXLj4yHGn0L wceJmi+004MUPPvq6fR8jd/iIlL2fUH6Ow53EdxEwDLnG416McJ6+2UhGJtzcVW7ln4OoT8Ir0+Lg CuOfXLe4prywY4BDV7X2qf+Bvvkq6ehlawumwrMhpR6JMvrOzmoB0HVU0EOXdxWA2JAn7k5T5C51b O7D/lgJGWC3w49pTiSqQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1q4yta-005yAn-0L; Fri, 02 Jun 2023 07:08:22 +0000 Received: from muru.com ([72.249.23.125]) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1q4ytX-005y9k-13 for linux-arm-kernel@lists.infradead.org; Fri, 02 Jun 2023 07:08:20 +0000 Received: from localhost (localhost [127.0.0.1]) by muru.com (Postfix) with ESMTPS id B9DAD8111; Fri, 2 Jun 2023 07:08:18 +0000 (UTC) Date: Fri, 2 Jun 2023 10:08:17 +0300 From: Tony Lindgren To: Nishanth Menon Cc: Conor Dooley , Krzysztof Kozlowski , Rob Herring , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Tero Kristo , Vignesh Raghavendra , Udit Kumar , Nitin Yadav , Neha Malcom Francis Subject: Re: [PATCH 2/6] arm64: dts: ti: k3-j721e: Configure pinctrl for timer IO Message-ID: <20230602070817.GI14287@atomide.com> References: <20230531213215.602395-1-nm@ti.com> <20230531213215.602395-3-nm@ti.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20230531213215.602395-3-nm@ti.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230602_000819_409714_705CB682 X-CRM114-Status: GOOD ( 12.38 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org * Nishanth Menon [230531 21:32]: > There are timer IO pads in the MCU domain, and in the MAIN domain. These > pads can be muxed for the related timers. > > There are timer IO control registers for input and output. The registers > for CTRLMMR_TIMER*_CTRL and CTRLMMR_MCU_TIMER*_CTRL are used to control > the input. The registers for CTCTRLMMR_TIMERIO*_CTRL and > CTRLMMR_MCU_TIMERIO*_CTRL the output. > > The multiplexing is documented in Technical Reference Manual[1] under > "Timer IO Muxing Control Registers" and "Timer IO Muxing Control > Registers", and the "Timers Overview" chapters. > > We do not expose the cascade_en bit due to the racy usage of > independent 32 bit registers in-line with the timer instantiation in > the device tree. The MCU timer controls are also marked as reserved for > usage by the MCU firmware. Reviewed-by: Tony Lindgren _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel