From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 916FFC04A94 for ; Wed, 19 Jul 2023 10:03:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230122AbjGSKDP (ORCPT ); Wed, 19 Jul 2023 06:03:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58908 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229972AbjGSKCp (ORCPT ); Wed, 19 Jul 2023 06:02:45 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9421C272B; Wed, 19 Jul 2023 03:02:22 -0700 (PDT) Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 36J9LVVh000685; Wed, 19 Jul 2023 10:02:18 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=zs2LESLuK5VHg11Qa9LDGUZVKIkqJy97YYGDZ2DCSXI=; b=S9um0/49V/ZDg0IgcRJ5mjV+qczXY2dz+VBx0NGBBtW1g8aSGYIDbFAKxeu417Patkst 2GF3dPDg73yAOmt0cLn1rdDMIhz/d84o9JpeZZE3hM3mBSHDC4DOeFjuu7j4q51/f1/b P5mIY4v3cpjD6HWYFJwqsuvfZLgH4Su2ncyZyvF5fSa2lDr2jVIJoJDFvijks5ORyvGm Y3OZNHVS9fusa0Qgz4ooIPh4wE3NpkBXVEmVtyT+uwnsMyiPtWlzozs72nZCE1XEIfMB kcFjt0FYp27EaxB2M33iuJv3D3b/bAKOStERI9QjxCh5AvszmNKmqr1WpT+NybuisYf2 cA== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3rwxknsksh-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 19 Jul 2023 10:02:18 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 36JA2HcM030399 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 19 Jul 2023 10:02:17 GMT Received: from tengfan2-gv.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Wed, 19 Jul 2023 03:02:13 -0700 From: Tengfei Fan To: , , , , CC: , , , , , , , , , Tengfei Fan Subject: [PATCH 1/5] arm64: dts: qcom: Add base SM4450 DTSI Date: Wed, 19 Jul 2023 18:01:31 +0800 Message-ID: <20230719100135.21325-2-quic_tengfan@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230719100135.21325-1-quic_tengfan@quicinc.com> References: <20230719100135.21325-1-quic_tengfan@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: z6cKSV_ptqhvcQlT-irTr7kDDVW06YJu X-Proofpoint-GUID: z6cKSV_ptqhvcQlT-irTr7kDDVW06YJu X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-19_06,2023-07-18_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 phishscore=0 spamscore=0 malwarescore=0 adultscore=0 impostorscore=0 mlxscore=0 lowpriorityscore=0 mlxlogscore=533 suspectscore=0 priorityscore=1501 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2307190091 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This add based DTSI for SM4450 SoC and includes base description of CPUs and interrupt-controller which helps to boot to shell with console on boards with this SoC. Signed-off-by: Tengfei Fan --- arch/arm64/boot/dts/qcom/sm4450.dtsi | 435 +++++++++++++++++++++++++++ 1 file changed, 435 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm4450.dtsi diff --git a/arch/arm64/boot/dts/qcom/sm4450.dtsi b/arch/arm64/boot/dts/qcom/sm4450.dtsi new file mode 100644 index 000000000000..ab14aecbdcea --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm4450.dtsi @@ -0,0 +1,435 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include + +/ { + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + clocks{ + xo_board: xo_board { + compatible = "fixed-clock"; + clock-frequency = <76800000>; + #clock-cells = <0>; + }; + + sleep_clk: sleep_clk { + compatible = "fixed-clock"; + clock-frequency = <32000>; + #clock-cells = <0>; + }; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; + #cooling-cells = <2>; + L2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&L3_0>; + L3_0: l3-cache { + compatible = "cache"; + cache-level = <3>; + cache-unified; + }; + }; + }; + + CPU1: cpu@100 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x100>; + enable-method = "psci"; + next-level-cache = <&L2_100>; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; + #cooling-cells = <2>; + L2_100: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&L3_0>; + }; + }; + + CPU2: cpu@200 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x200>; + enable-method = "psci"; + next-level-cache = <&L2_200>; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; + #cooling-cells = <2>; + L2_200: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&L3_0>; + }; + }; + + CPU3: cpu@300 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x300>; + enable-method = "psci"; + next-level-cache = <&L2_300>; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; + #cooling-cells = <2>; + L2_300: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&L3_0>; + }; + }; + + CPU4: cpu@400 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x400>; + enable-method = "psci"; + next-level-cache = <&L2_400>; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; + #cooling-cells = <2>; + L2_400: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&L3_0>; + }; + }; + + CPU5: cpu@500 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x500>; + enable-method = "psci"; + next-level-cache = <&L2_500>; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; + #cooling-cells = <2>; + L2_500: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&L3_0>; + }; + }; + + CPU6: cpu@600 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x600>; + enable-method = "psci"; + next-level-cache = <&L2_600>; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; + #cooling-cells = <2>; + L2_600: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&L3_0>; + }; + }; + + CPU7: cpu@700 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x700>; + enable-method = "psci"; + next-level-cache = <&L2_700>; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; + #cooling-cells = <2>; + L2_700: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&L3_0>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + + core4 { + cpu = <&CPU4>; + }; + + core5 { + cpu = <&CPU5>; + }; + }; + + cluster1 { + core6 { + cpu = <&CPU6>; + }; + + core7 { + cpu = <&CPU7>; + }; + }; + }; + + idle-states { + entry-method = "psci"; + + LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { + compatible = "arm,idle-state"; + idle-state-name = "silver-rail-power-collapse"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <800>; + exit-latency-us = <750>; + min-residency-us = <4090>; + local-timer-stop; + }; + + BIG_CPU_SLEEP_0: cpu-sleep-1-0 { + compatible = "arm,idle-state"; + idle-state-name = "gold-rail-power-collapse"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <600>; + exit-latency-us = <1550>; + min-residency-us = <4791>; + local-timer-stop; + }; + }; + + domain-idle-states { + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x41000044>; + entry-latency-us = <1050>; + exit-latency-us = <2500>; + min-residency-us = <5309>; + }; + + CLUSTER_SLEEP_1: cluster-sleep-1 { + compatible = "domain-idle-state"; + idle-state-name = "cluster-power-collapse"; + arm,psci-suspend-param = <0x41003344>; + entry-latency-us = <1561>; + exit-latency-us = <2801>; + min-residency-us = <8550>; + }; + }; + }; + + firmware { + scm: scm { + compatible = "qcom,scm-sm4450", "qcom,scm"; + #reset-cells = <1>; + }; + }; + + memory@a0000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the size */ + reg = <0x0 0xa0000000 0x0 0x0>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + + CPU_PD0: power-domain-cpu0 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD1: power-domain-cpu1 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD2: power-domain-cpu2 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD3: power-domain-cpu3 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD4: power-domain-cpu4 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD5: power-domain-cpu5 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD6: power-domain-cpu6 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD7: power-domain-cpu7 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CLUSTER_PD: power-domain-cpu-cluster0 { + #power-domain-cells = <0>; + domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>; + }; + }; + + soc: soc@0 { + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0 0 0 0x10 0>; + dma-ranges = <0 0 0 0 0x10 0>; + compatible = "simple-bus"; + + tcsr_mutex: hwlock@1f40000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x0 0x01f40000 0x0 0x40000>; + #hwlock-cells = <1>; + }; + + pdc: interrupt-controller@b220000 { + compatible = "qcom,sm4450-pdc", "qcom,pdc"; + reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; + qcom,pdc-ranges = <0 480 94>, <94 494 31>, <125 63 1>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + + intc: interrupt-controller@17200000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-controller; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x20000>; + reg = <0x0 0x17200000 0x0 0x10000>, /* GICD */ + <0x0 0x17260000 0x0 0x100000>; /* GICR * 8 */ + interrupts = ; + }; + + timer@17420000 { + compatible = "arm,armv7-timer-mem"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0x20000000>; + reg = <0x0 0x17420000 0x0 0x1000>; + clock-frequency = <19200000>; + + frame@17421000 { + frame-number = <0>; + interrupts = , + ; + reg = <0x17421000 0x1000>, + <0x17422000 0x1000>; + }; + + frame@17423000 { + frame-number = <1>; + interrupts = ; + reg = <0x17423000 0x1000>; + status = "disabled"; + }; + + frame@17425000 { + frame-number = <2>; + interrupts = ; + reg = <0x17425000 0x1000>; + status = "disabled"; + }; + + frame@17427000 { + frame-number = <3>; + interrupts = ; + reg = <0x17427000 0x1000>; + status = "disabled"; + }; + + frame@17429000 { + frame-number = <4>; + interrupts = ; + reg = <0x17429000 0x1000>; + status = "disabled"; + }; + + frame@1742b000 { + frame-number = <5>; + interrupts = ; + reg = <0x1742b000 0x1000>; + status = "disabled"; + }; + + frame@1742d000 { + frame-number = <6>; + interrupts = ; + reg = <0x1742d000 0x1000>; + status = "disabled"; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + clock-frequency = <19200000>; + }; +}; -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project