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* [PATCH] RISC-V: Remove ptrace support for vectors
@ 2023-08-10 21:48 Palmer Dabbelt
  2023-08-12 17:12 ` Maciej W. Rozycki
  2023-08-23 19:40 ` patchwork-bot+linux-riscv
  0 siblings, 2 replies; 3+ messages in thread
From: Palmer Dabbelt @ 2023-08-10 21:48 UTC (permalink / raw)
  To: linux-riscv, andy.chiu; +Cc: Palmer Dabbelt

We've found two bugs here: NT_RISCV_VECTOR steps on NT_RISCV_CSR (which
is only for embedded), and we don't have vlenb in the core dumps.  Given
that we've have a pair of bugs croup up as part of the GDB review we've
probably got other issues, so let's just cut this for 6.5 and get it
right.

Fixes: 0c59922c769a ("riscv: Add ptrace vector support")
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
---
 arch/riscv/kernel/ptrace.c | 69 --------------------------------------
 include/uapi/linux/elf.h   |  1 -
 2 files changed, 70 deletions(-)

diff --git a/arch/riscv/kernel/ptrace.c b/arch/riscv/kernel/ptrace.c
index 1d572cf3140f..487303e3ef22 100644
--- a/arch/riscv/kernel/ptrace.c
+++ b/arch/riscv/kernel/ptrace.c
@@ -25,9 +25,6 @@ enum riscv_regset {
 #ifdef CONFIG_FPU
 	REGSET_F,
 #endif
-#ifdef CONFIG_RISCV_ISA_V
-	REGSET_V,
-#endif
 };
 
 static int riscv_gpr_get(struct task_struct *target,
@@ -84,61 +81,6 @@ static int riscv_fpr_set(struct task_struct *target,
 }
 #endif
 
-#ifdef CONFIG_RISCV_ISA_V
-static int riscv_vr_get(struct task_struct *target,
-			const struct user_regset *regset,
-			struct membuf to)
-{
-	struct __riscv_v_ext_state *vstate = &target->thread.vstate;
-
-	if (!riscv_v_vstate_query(task_pt_regs(target)))
-		return -EINVAL;
-
-	/*
-	 * Ensure the vector registers have been saved to the memory before
-	 * copying them to membuf.
-	 */
-	if (target == current)
-		riscv_v_vstate_save(current, task_pt_regs(current));
-
-	/* Copy vector header from vstate. */
-	membuf_write(&to, vstate, offsetof(struct __riscv_v_ext_state, datap));
-	membuf_zero(&to, sizeof(vstate->datap));
-
-	/* Copy all the vector registers from vstate. */
-	return membuf_write(&to, vstate->datap, riscv_v_vsize);
-}
-
-static int riscv_vr_set(struct task_struct *target,
-			const struct user_regset *regset,
-			unsigned int pos, unsigned int count,
-			const void *kbuf, const void __user *ubuf)
-{
-	int ret, size;
-	struct __riscv_v_ext_state *vstate = &target->thread.vstate;
-
-	if (!riscv_v_vstate_query(task_pt_regs(target)))
-		return -EINVAL;
-
-	/* Copy rest of the vstate except datap */
-	ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, vstate, 0,
-				 offsetof(struct __riscv_v_ext_state, datap));
-	if (unlikely(ret))
-		return ret;
-
-	/* Skip copy datap. */
-	size = sizeof(vstate->datap);
-	count -= size;
-	ubuf += size;
-
-	/* Copy all the vector registers. */
-	pos = 0;
-	ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, vstate->datap,
-				 0, riscv_v_vsize);
-	return ret;
-}
-#endif
-
 static const struct user_regset riscv_user_regset[] = {
 	[REGSET_X] = {
 		.core_note_type = NT_PRSTATUS,
@@ -158,17 +100,6 @@ static const struct user_regset riscv_user_regset[] = {
 		.set = riscv_fpr_set,
 	},
 #endif
-#ifdef CONFIG_RISCV_ISA_V
-	[REGSET_V] = {
-		.core_note_type = NT_RISCV_VECTOR,
-		.align = 16,
-		.n = ((32 * RISCV_MAX_VLENB) +
-		      sizeof(struct __riscv_v_ext_state)) / sizeof(__u32),
-		.size = sizeof(__u32),
-		.regset_get = riscv_vr_get,
-		.set = riscv_vr_set,
-	},
-#endif
 };
 
 static const struct user_regset_view riscv_user_native_view = {
diff --git a/include/uapi/linux/elf.h b/include/uapi/linux/elf.h
index 0c8cf359ea5b..e0e159138331 100644
--- a/include/uapi/linux/elf.h
+++ b/include/uapi/linux/elf.h
@@ -443,7 +443,6 @@ typedef struct elf64_shdr {
 #define NT_MIPS_DSP	0x800		/* MIPS DSP ASE registers */
 #define NT_MIPS_FP_MODE	0x801		/* MIPS floating-point mode */
 #define NT_MIPS_MSA	0x802		/* MIPS SIMD registers */
-#define NT_RISCV_VECTOR	0x900		/* RISC-V vector registers */
 #define NT_LOONGARCH_CPUCFG	0xa00	/* LoongArch CPU config registers */
 #define NT_LOONGARCH_CSR	0xa01	/* LoongArch control and status registers */
 #define NT_LOONGARCH_LSX	0xa02	/* LoongArch Loongson SIMD Extension registers */
-- 
2.41.0


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^ permalink raw reply related	[flat|nested] 3+ messages in thread

* Re: [PATCH] RISC-V: Remove ptrace support for vectors
  2023-08-10 21:48 [PATCH] RISC-V: Remove ptrace support for vectors Palmer Dabbelt
@ 2023-08-12 17:12 ` Maciej W. Rozycki
  2023-08-23 19:40 ` patchwork-bot+linux-riscv
  1 sibling, 0 replies; 3+ messages in thread
From: Maciej W. Rozycki @ 2023-08-12 17:12 UTC (permalink / raw)
  To: Palmer Dabbelt; +Cc: linux-riscv, andy.chiu

On Thu, 10 Aug 2023, Palmer Dabbelt wrote:

> We've found two bugs here: NT_RISCV_VECTOR steps on NT_RISCV_CSR (which
> is only for embedded), and we don't have vlenb in the core dumps.  Given
> that we've have a pair of bugs croup up as part of the GDB review we've
> probably got other issues, so let's just cut this for 6.5 and get it
> right.

 It might be worth mentioning that vlenb isn't there in ptrace(2) either, 
but otherwise:

Reviewed-by: Maciej W. Rozycki <macro@orcam.me.uk>

  Maciej

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http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 3+ messages in thread

* Re: [PATCH] RISC-V: Remove ptrace support for vectors
  2023-08-10 21:48 [PATCH] RISC-V: Remove ptrace support for vectors Palmer Dabbelt
  2023-08-12 17:12 ` Maciej W. Rozycki
@ 2023-08-23 19:40 ` patchwork-bot+linux-riscv
  1 sibling, 0 replies; 3+ messages in thread
From: patchwork-bot+linux-riscv @ 2023-08-23 19:40 UTC (permalink / raw)
  To: Palmer Dabbelt; +Cc: linux-riscv, andy.chiu

Hello:

This patch was applied to riscv/linux.git (fixes)
by Palmer Dabbelt <palmer@rivosinc.com>:

On Thu, 10 Aug 2023 14:48:10 -0700 you wrote:
> We've found two bugs here: NT_RISCV_VECTOR steps on NT_RISCV_CSR (which
> is only for embedded), and we don't have vlenb in the core dumps.  Given
> that we've have a pair of bugs croup up as part of the GDB review we've
> probably got other issues, so let's just cut this for 6.5 and get it
> right.
> 
> Fixes: 0c59922c769a ("riscv: Add ptrace vector support")
> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
> 
> [...]

Here is the summary with links:
  - RISC-V: Remove ptrace support for vectors
    https://git.kernel.org/riscv/c/e3f9324b231a

You are awesome, thank you!
-- 
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html



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^ permalink raw reply	[flat|nested] 3+ messages in thread

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Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
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2023-08-10 21:48 [PATCH] RISC-V: Remove ptrace support for vectors Palmer Dabbelt
2023-08-12 17:12 ` Maciej W. Rozycki
2023-08-23 19:40 ` patchwork-bot+linux-riscv

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