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From: Jisheng Zhang <jszhang@kernel.org>
To: Guo Ren <guoren@kernel.org>, Fu Wei <wefu@redhat.com>,
	Conor Dooley <conor@kernel.org>, Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>
Cc: inux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org
Subject: [PATCH] riscv: dts: thead: set dma-noncoherent to soc bus
Date: Sun, 20 Aug 2023 19:53:53 +0800	[thread overview]
Message-ID: <20230820115353.1962-1-jszhang@kernel.org> (raw)

riscv select ARCH_DMA_DEFAULT_COHERENT by default, and th1520 isn't
dma coherent, so set dma-noncoherent to reflect this fact.

Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
---
 arch/riscv/boot/dts/thead/th1520.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
index 56a73134b49e..58108f0eb3fd 100644
--- a/arch/riscv/boot/dts/thead/th1520.dtsi
+++ b/arch/riscv/boot/dts/thead/th1520.dtsi
@@ -139,6 +139,7 @@ soc {
 		interrupt-parent = <&plic>;
 		#address-cells = <2>;
 		#size-cells = <2>;
+		dma-noncoherent;
 		ranges;
 
 		plic: interrupt-controller@ffd8000000 {
-- 
2.40.1


             reply	other threads:[~2023-08-20 12:08 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-08-20 11:53 Jisheng Zhang [this message]
2023-08-20 12:04 ` [PATCH] riscv: dts: thead: set dma-noncoherent to soc bus Jisheng Zhang
2023-08-20 12:04   ` Jisheng Zhang
2023-09-03 23:32 ` Drew Fustini
2023-09-04 14:45   ` Jisheng Zhang
2023-09-04 16:28     ` Xi Ruoyao
2023-09-04 17:52       ` Drew Fustini
2023-09-04 17:52         ` Drew Fustini
2023-09-04 19:27         ` Drew Fustini
2023-09-04 19:27           ` Drew Fustini
2023-09-04 18:50     ` Drew Fustini
2023-09-04 18:50       ` Drew Fustini

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