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* [PATCH] riscv: dts: thead: set dma-noncoherent to soc bus
@ 2023-08-20 11:53 Jisheng Zhang
  2023-08-20 12:04   ` Jisheng Zhang
  2023-09-03 23:32 ` Drew Fustini
  0 siblings, 2 replies; 12+ messages in thread
From: Jisheng Zhang @ 2023-08-20 11:53 UTC (permalink / raw)
  To: Guo Ren, Fu Wei, Conor Dooley, Rob Herring, Krzysztof Kozlowski,
	Paul Walmsley, Palmer Dabbelt, Albert Ou
  Cc: inux-riscv, devicetree, linux-kernel

riscv select ARCH_DMA_DEFAULT_COHERENT by default, and th1520 isn't
dma coherent, so set dma-noncoherent to reflect this fact.

Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
---
 arch/riscv/boot/dts/thead/th1520.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
index 56a73134b49e..58108f0eb3fd 100644
--- a/arch/riscv/boot/dts/thead/th1520.dtsi
+++ b/arch/riscv/boot/dts/thead/th1520.dtsi
@@ -139,6 +139,7 @@ soc {
 		interrupt-parent = <&plic>;
 		#address-cells = <2>;
 		#size-cells = <2>;
+		dma-noncoherent;
 		ranges;
 
 		plic: interrupt-controller@ffd8000000 {
-- 
2.40.1


^ permalink raw reply related	[flat|nested] 12+ messages in thread

end of thread, other threads:[~2023-09-04 19:28 UTC | newest]

Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-08-20 11:53 [PATCH] riscv: dts: thead: set dma-noncoherent to soc bus Jisheng Zhang
2023-08-20 12:04 ` Jisheng Zhang
2023-08-20 12:04   ` Jisheng Zhang
2023-09-03 23:32 ` Drew Fustini
2023-09-04 14:45   ` Jisheng Zhang
2023-09-04 16:28     ` Xi Ruoyao
2023-09-04 17:52       ` Drew Fustini
2023-09-04 17:52         ` Drew Fustini
2023-09-04 19:27         ` Drew Fustini
2023-09-04 19:27           ` Drew Fustini
2023-09-04 18:50     ` Drew Fustini
2023-09-04 18:50       ` Drew Fustini

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