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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id n10-20020a05600c4f8a00b004053e9276easm18736143wmq.32.2023.12.04.06.33.23 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Dec 2023 06:33:23 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 0/1] target-arm queue Date: Mon, 4 Dec 2023 14:33:21 +0000 Message-Id: <20231204143322.837136-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Just one fix for rc3. Technically this isn't a regression since 8.1, but it is a small change that avoids the user being able to select an oddball combination of CPU features that currently QEMU will assert on. thanks -- PMM The following changes since commit 29b5d70cb70574b499517ec9e9f80dea496a3cc0: Merge tag 'pull-ppc-for-8.2-20231130' of https://gitlab.com/npiggin/qemu into staging (2023-12-01 07:29:52 -0500) are available in the Git repository at: https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20231204-1 for you to fetch changes up to f7767ca301796334f74b9b642b395a4bd3e3dbac: target/arm: Disable SME if SVE is disabled (2023-12-04 13:34:16 +0000) ---------------------------------------------------------------- target-arm queue: * Turn off SME if SVE is turned off (this combination doesn't currently work and QEMU will assert if you try it) ---------------------------------------------------------------- Peter Maydell (1): target/arm: Disable SME if SVE is disabled target/arm/cpu.c | 10 ++++++++++ 1 file changed, 10 insertions(+)