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[73.169.12.54]) by smtp.gmail.com with ESMTPSA id q3-20020a92c003000000b00361b6a1e6aasm3152089ild.87.2024.02.01.02.33.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Feb 2024 02:33:41 -0800 (PST) From: Taylor Simpson To: qemu-devel@nongnu.org Cc: bcain@quicinc.com, quic_mathbern@quicinc.com, sidneym@quicinc.com, quic_mliebel@quicinc.com, richard.henderson@linaro.org, philmd@linaro.org, ale@rev.ng, anjo@rev.ng, ltaylorsimpson@gmail.com Subject: [PATCH v2 0/3] Hexagon (target/hexagon) Enable more short-circuit packets Date: Thu, 1 Feb 2024 03:33:37 -0700 Message-Id: <20240201103340.119081-1-ltaylorsimpson@gmail.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::12e; envelope-from=ltaylorsimpson@gmail.com; helo=mail-il1-x12e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This patch series improves the set of packets that can short-circuit the commit packet logic and write the results directly during the execution of each instruction in the packet. The key observation is that checking for overlap between register reads and writes is different from read-after-write. For example, this packet { R0 = add(R0,R1); R6 = add(R6,R7) } has an overlap between the reads and writes without doing a read after a write. Therefore, it is safe to write directly into the destination registers during instruction execution. Another example is a .new register read. These can read from either the destination register or a temporary location. HVX instructions with generated helpers require special handling. The semantics of the helpers are pass-by-reference, so we still need the overlap check for these. ***** Changes in v2 ***** Conform to object oriented generators patch https://lists.gnu.org/archive/html/qemu-devel/2023-12/msg01211.html Taylor Simpson (3): Hexagon (target/hexagon) Analyze reads before writes Hexagon (target/hexagon) Enable more short-circuit packets (scalar core) Hexagon (target/hexagon) Enable more short-circuit packets (HVX) target/hexagon/translate.h | 119 +++++++++++++++++++++++----- target/hexagon/translate.c | 77 ++---------------- target/hexagon/README | 9 ++- target/hexagon/gen_analyze_funcs.py | 55 ++++++++----- target/hexagon/hex_common.py | 98 +++++++++++++---------- 5 files changed, 200 insertions(+), 158 deletions(-) -- 2.34.1