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[83.9.31.12]) by smtp.gmail.com with ESMTPSA id lg25-20020a170907181900b00a3c1e1ca800sm973242ejc.11.2024.02.10.09.10.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 10 Feb 2024 09:10:14 -0800 (PST) From: Konrad Dybcio Date: Sat, 10 Feb 2024 18:10:06 +0100 Subject: [PATCH v2 2/3] PCI: qcom: Read back PARF_LTSSM register Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20240210-topic-8280_pcie-v2-2-1cef4b606883@linaro.org> References: <20240210-topic-8280_pcie-v2-0-1cef4b606883@linaro.org> In-Reply-To: <20240210-topic-8280_pcie-v2-0-1cef4b606883@linaro.org> To: Bjorn Andersson , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Philipp Zabel Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Johan Hovold , Konrad Dybcio X-Mailer: b4 0.13-dev-0438c To ensure write completion, read the PARF_LTSSM register after setting the LTSSM enable bit before polling for "link up". Reviewed-by: Manivannan Sadhasivam Signed-off-by: Konrad Dybcio --- drivers/pci/controller/dwc/pcie-qcom.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index cbde9effa352..6a469ed213ce 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -539,6 +539,7 @@ static void qcom_pcie_2_3_2_ltssm_enable(struct qcom_pcie *pcie) val = readl(pcie->parf + PARF_LTSSM); val |= LTSSM_EN; writel(val, pcie->parf + PARF_LTSSM); + readl(pcie->parf + PARF_LTSSM); } static int qcom_pcie_get_resources_2_3_2(struct qcom_pcie *pcie) -- 2.40.1