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q=dns/txt; c=relaxed/relaxed; d=haloniitty.fi; s=default; h=Content-Type:MIME-Version:References: In-Reply-To:Message-ID:Subject:Cc:To:From:Date:Sender:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id: List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=JaeyaROe1f4Zrix0WXESY3j/JYRuGeJy+nfml8UVj0o=; b=csbnNj6LDlHtGWbxK+6qA8KJp4 3d/ocxTJNfXcBmIWX5076xJ9Bfbv1dM+acIEu4h/gDCzX3bcXH2BM4KEZkx33jFHOGcPUt7UcG8Ww VQiZn3n2EnAjjzuLOupOXFtR+rX3U2s8ZSuTqvhc+txC2VYM7oatB1safji+7H0FHJP1/yMW6Mwv5 s/71gDiuHyrCVNwjcH2s2gKSnd8H2jC9skZAHMYG6PZvid87tUwTa2lBhYKSlrqX4Q8oG5aiXajIe 5fr+Mtxzc1xnoaVUQy715zzwr6KK4P9AHVFWFZUvwkM4ezduM2E8NB9nAFnUMTjvcxI3eftjncCaQ VABRR/oA==; Received: from [194.136.85.206] (port=34518 helo=eldfell) by whm50.louhi.net with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.96.2) (envelope-from ) id 1rc2MO-0002I0-1P; Mon, 19 Feb 2024 14:03:01 +0200 Date: Mon, 19 Feb 2024 14:02:51 +0200 From: Pekka Paalanen To: "Shankar, Uma" Cc: "ville.syrjala@linux.intel.com" , "intel-gfx@lists.freedesktop.org" , "dri-devel@lists.freedesktop.org" , "contact@emersion.fr" , "harry.wentland@amd.com" , "mwen@igalia.com" , "jadahl@redhat.com" , "sebastian.wick@redhat.com" , "shashank.sharma@amd.com" , "agoins@nvidia.com" , "joshua@froggi.es" , "mdaenzer@redhat.com" , "aleixpol@kde.org" , "xaver.hugl@gmail.com" , "victoria@system76.com" , "daniel@ffwll.ch" , "quic_naseer@quicinc.com" , "quic_cbraga@quicinc.com" , "quic_abhinavk@quicinc.com" , "arthurgrillo@riseup.net" , "marcan@marcan.st" , "Liviu.Dudau@arm.com" , "sashamcintosh@google.com" , "sean@poorly.run" Subject: Re: [PATCH 17/28] drm/i915: Define segmented Lut and add capabilities to colorop Message-ID: <20240219140251.59d730cd@eldfell> In-Reply-To: References: <20240213064835.139464-1-uma.shankar@intel.com> <20240213064835.139464-18-uma.shankar@intel.com> <20240213113727.22f9c8e5@eldfell> <20240214110340.477e9df3@eldfell> X-Mailer: Claws Mail 4.1.1 (GTK 3.24.38; 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charset=US-ASCII Content-Transfer-Encoding: quoted-printable On Mon, 19 Feb 2024 10:34:19 +0000 "Shankar, Uma" wrote: > > -----Original Message----- > > From: Pekka Paalanen > > Sent: Wednesday, February 14, 2024 2:34 PM > > To: Shankar, Uma > > Cc: ville.syrjala@linux.intel.com; intel-gfx@lists.freedesktop.org; dri- > > devel@lists.freedesktop.org; contact@emersion.fr; harry.wentland@amd.co= m; > > mwen@igalia.com; jadahl@redhat.com; sebastian.wick@redhat.com; > > shashank.sharma@amd.com; agoins@nvidia.com; joshua@froggi.es; > > mdaenzer@redhat.com; aleixpol@kde.org; xaver.hugl@gmail.com; > > victoria@system76.com; daniel@ffwll.ch; quic_naseer@quicinc.com; > > quic_cbraga@quicinc.com; quic_abhinavk@quicinc.com; arthurgrillo@riseup= .net; > > marcan@marcan.st; Liviu.Dudau@arm.com; sashamcintosh@google.com; > > sean@poorly.run > > Subject: Re: [PATCH 17/28] drm/i915: Define segmented Lut and add capab= ilities > > to colorop > >=20 > > On Wed, 14 Feb 2024 07:28:37 +0000 > > "Shankar, Uma" wrote: > > =20 > > > > -----Original Message----- > > > > From: dri-devel On Behalf > > > > Of Pekka Paalanen > > > > Sent: Tuesday, February 13, 2024 3:07 PM > > > > To: Shankar, Uma > > > > Cc: intel-gfx@lists.freedesktop.org; > > > > dri-devel@lists.freedesktop.org; ville.syrjala@linux.intel.com; > > > > contact@emersion.fr; harry.wentland@amd.com; mwen@igalia.com; > > > > jadahl@redhat.com; sebastian.wick@redhat.com; > > > > shashank.sharma@amd.com; agoins@nvidia.com; joshua@froggi.es; > > > > mdaenzer@redhat.com; aleixpol@kde.org; xaver.hugl@gmail.com; > > > > victoria@system76.com; daniel@ffwll.ch; quic_naseer@quicinc.com; > > > > quic_cbraga@quicinc.com; quic_abhinavk@quicinc.com; > > > > arthurgrillo@riseup.net; marcan@marcan.st; Liviu.Dudau@arm.com; > > > > sashamcintosh@google.com; sean@poorly.run > > > > Subject: Re: [PATCH 17/28] drm/i915: Define segmented Lut and add > > > > capabilities to colorop > > > > > > > > On Tue, 13 Feb 2024 12:18:24 +0530 > > > > Uma Shankar wrote: > > > > =20 > > > > > This defines the lut segments and create the color pipeline > > > > > > > > > > Signed-off-by: Uma Shankar > > > > > Signed-off-by: Chaitanya Kumar Borah > > > > > > > > > > --- > > > > > drivers/gpu/drm/i915/display/intel_color.c | 109 > > > > > +++++++++++++++++++++ > > > > > 1 file changed, 109 insertions(+) > > > > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_color.c > > > > > b/drivers/gpu/drm/i915/display/intel_color.c > > > > > index e223edbe4c13..223cd1ff7291 100644 > > > > > --- a/drivers/gpu/drm/i915/display/intel_color.c > > > > > +++ b/drivers/gpu/drm/i915/display/intel_color.c > > > > > @@ -3811,6 +3811,105 @@ static const struct intel_color_funcs =20 > > > > ilk_color_funcs =3D { =20 > > > > > .get_config =3D ilk_get_config, > > > > > }; > > > > > > > > > > +static const struct drm_color_lut_range xelpd_degamma_hdr[] =3D { > > > > > + /* segment 1 */ > > > > > + { > > > > > + .flags =3D (DRM_MODE_LUT_REFLECT_NEGATIVE | > > > > > + DRM_MODE_LUT_INTERPOLATE | > > > > > + DRM_MODE_LUT_NON_DECREASING), =20 > > > > > > > > Hi Uma, > > > > > > > > is it a good idea to have these flags per-segment? > > > > > > > > I would find it very strange, unusable really, if REFLECT_NEGATIVE > > > > applied on some but not all segments, for example. Is such > > > > flexibility really necessary in the hardware description? =20 > > > > > > Hi Pekka, > > > Idea to have these flags is to just have some option in case there are > > > some differences across segments. Most cases this should not be the > > > case, just helps to future proof the implementation. > > > > > > Based on how the community feels on the usability of it, we can take a > > > call on the flags and the expected interpretation for the same. We ar= e open for =20 > > suggestions on the same. =20 > > > =20 > > > > =20 > > > > > + .count =3D 128, > > > > > + .input_bpc =3D 24, .output_bpc =3D 16, =20 > > > > > > > > The same question about input_bpc and output_bpc. =20 > > > > > > Same for these as well, userspace can just ignore these if no usage. > > > However, for some clients it may help in Lut computations. > > > The original idea for the structure came from Ville (missed to mention > > > that in cover letter, will get that updated in next version). > > > > > > @ville.syrjala@linux.intel.com Please share your inputs on the usabil= ity of these =20 > > attributes. > >=20 > > Userspace will always need to evaluate whether each segment is good eno= ugh > > individually, so maybe it's not that big deal. > >=20 > > Ignoring these is not an option for userspace, because that would mean = userspace > > does not know what it is getting. If UAPI contains a parameter, then th= e onus is on > > userspace to ensure the value is acceptable. =20 >=20 > Got your point, the parameters, and expectations with it should be clearl= y defined. > Here it just means what is the bpc which is fed to the color block and at= what bpc > results come out after rounding and truncation. This information may help= in > computing the LUT co-efficients and get better accuracy. >=20 > Having said that, we are not using it as of now in the IGT tests. We can = discuss the > usability and usefulness of this attribute for userspace, based on recomm= endation > we can adopt or drop this. Hi Uma, this discussion applies much more to the flags than bpc. Bpc is interesting to userspace, so I do think it should be kept, and extended to all colorops as possible. > > > > > + .input_bpc =3D 24, .output_bpc =3D 16, =20 > > > > > + .start =3D 0, .end =3D (1 << 24) - 1, > > > > > + .min =3D 0, .max =3D (1 << 24) - 1, Btw. does this say, that normalized input value range is [0.0, 1.0], and output values must be in [0.0, 256.0]? That the divisor is (1 << bpc) - 1, and not (1 << bpc)? > > > > > + }, > > > > > + /* segment 2 */ > > > > > + { > > > > > + .flags =3D (DRM_MODE_LUT_REFLECT_NEGATIVE | > > > > > + DRM_MODE_LUT_INTERPOLATE | > > > > > + DRM_MODE_LUT_REUSE_LAST | > > > > > + DRM_MODE_LUT_NON_DECREASING), > > > > > + .count =3D 1, > > > > > + .input_bpc =3D 24, .output_bpc =3D 16, > > > > > + .start =3D (1 << 24) - 1, .end =3D 1 << 24, =20 > > > > > > > > What if there is a gap or overlap between the previous segment .end > > > > and the next segment .start? Is it forbidden? Will the kernel common > > > > code verify that drivers don't make mistakes? Or IGT? =20 > > > > > > This is just to help give some reference to userspace. As of now, > > > driver trusts the values coming from userspace if it sends wrong valu= es its on =20 > > him and driver can't help much. =20 > > > However, we surely can have some sanity check like non decreasing lut= s etc. to =20 > > driver. > >=20 > > But what will guarantee that the driver provided values are consistent? > > That they actually describe a template of a well-formed sampled curve? = If they > > are not consistent, userspace cannot use the colorop. > > Whose responsibility is it to ensure the consistency? =20 >=20 > Since the driver will be privileged, I guess userspace should believe the= values are > sane as reported by the properties. This is as for any other hardware cap= abilities. > Also, its immutable so userspace will not be able to tweak it making it s= afe. It is still possible for the driver to give an utter nonsense blob. Where should be the tests to prevent that, in IGT or DRM core? > > We have a few examples of drivers getting descriptive values like these= simply > > wrong until DRM common code started sanity-checking them, the bitmasks = of > > possible_clones and possible_crtcs for example. =20 >=20 > We can implement some helpers to catch basic abnormalities with LUT repor= ting > while property creation itself. Like decreasing luts, not matching the r= eported flags etc. I really meant *drivers* getting the *advertisement* values wrong. Claiming that a connector/encoder is compatible with CRTC index 17 when such CRTC does not exist is a real example. Or that all connectors can be clones with all other connectors, even those that do not exist. In the case of segmented LUTs, there could be these mistakes for a two-segment { A, B } description: - segment A has REFLECT_NEGATIVE, but segment B does not - segment B normalised start is smaller than segment A normalised end - there is a gap between segment A normalised end and segment B normalised = start - segment A normalised max is smaller than segment B normalised min - segment sample count is zero (or negative) - segment max is smaller than segment min And so on. Something needs to check for these and catch these, before a driver with them is released or even merged. Think of it as reversed checks at UAPI boundary where a common component is checking that drivers get it right. >=20 > > There should also be DRM common code to verify that userspace provided = data > > matches the segmented LUT description rather than drivers just trusting= it. If it > > doesn't match, the atomic commit must fail rather than silently malfunc= tion. The > > same with programming hardware: if hardware does not produce the intend= ed > > result from a given segmented LUT configuration, the atomic commit must= fail > > instead of malfunction. =20 >=20 > Yes, we can have some checks in driver for sanity of userspace provided v= alues. > Things like LUTs not following the flags and capabilities reported, going= beyond > the range etc. However the actual values and computation of the same has = to be > userspace responsibility, if the co-efficients go wrong then responsibili= ty of the artifact > should be on the client/compositor who is controlling it (permission can = be controlled > so that only allowed userspace can be able to change color setttings) Naturally. A driver cannot know if the values are correct for what userspace intends to do, but the DRM core can check that the values fit the segmented LUT description that the driver advertised. Permission? Permissions are already controlled by the DRM master mechanic. > > > > > > Ideally LUT values should not overlap, but we can indicate this > > > explicitly with flag to hint the userspace (for overlap or otherwise)= and also get =20 > > a check in driver for the same. > >=20 > > Sorry? How could overlapping segments ever work? Or segments with a gap > > between them? =20 >=20 > I have not seen overlapping luts in segments, we can take a call if all v= endors align. >=20 > > If segments overlap, what's the rule for choosing which segment to use = for an > > input value hitting both? The segments can disagree on the result. > >=20 > > If there are gaps, what is the rule how to handle an input value hittin= g a gap? =20 >=20 > This can be brainstormed, if any usescase like this exists. These questions were supposed to make you think and realise that overlapping/gapped segments make absolutely no sense at all by pointing out the problems they would cause as an interface description. Even if hardware had literally overlapping segments, then the driver should advertise non-overlapping segments that match what the hardware will achieve. If hardware had literally gaps between segments, then... either the hardware cannot be fully used, or the driver will manufacture a description without gaps that matches hardware behaviour. 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