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Tue, 05 Mar 2024 09:49:14 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 4259nDpM027674 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 5 Mar 2024 09:49:13 GMT Received: from hu-krichai-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Tue, 5 Mar 2024 01:49:09 -0800 From: Krishna chaitanya chundru Date: Tue, 5 Mar 2024 15:19:01 +0530 Subject: [PATCH v2] PCI: dwc: Enable runtime pm of the host bridge Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-ID: <20240305-runtime_pm_enable-v2-1-a849b74091d1@quicinc.com> X-B4-Tracking: v=1; b=H4sIAI7q5mUC/32NWw6CMBBFt0Lm25pOeRj8Yh+GEGhHmUQKttBoS PduZQF+npPcc3fw5Jg8XLMdHAX2PNsE6pSBHnv7IMEmMSipCqmwFm6zK0/ULVNHth+eJAaj8VJ jMZhSQtotju78Ppq3NvHIfp3d57gI+LP/agEFCpPXVSVzlKUsmtfGmq0+63mCNsb4BdVSMm60A AAA To: Jingoo Han , Gustavo Pimentel , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas CC: , , , , , , , Krishna chaitanya chundru X-Mailer: b4 0.13-dev-83828 X-Developer-Signature: v=1; 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PCIe controller(Top level parent & parent of host bridge) | v PCIe Host bridge(Parent of PCI-PCI bridge) | v PCI-PCI bridge(Parent of endpoint driver) | v PCIe endpoint driver Since runtime PM is disabled for host bridge, the state of the child devices under the host bridge is not taken into account by PM framework for the top level parent, PCIe controller. So PM framework, allows the controller driver to enter runtime PM irrespective of the state of the devices under the host bridge. And this causes the topology breakage and also possible PM issues. So enable pm runtime for the host bridge, so that controller driver goes to suspend only when all child devices goes to runtime suspend. Signed-off-by: Krishna chaitanya chundru --- Changes in v2: - Updated commit message as suggested by mani. - Link to v1: https://lore.kernel.org/r/20240219-runtime_pm_enable-v1-1-d39660310504@quicinc.com --- drivers/pci/controller/dwc/pcie-designware-host.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index d5fc31f8345f..57756a73df30 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -16,6 +16,7 @@ #include #include #include +#include #include "../../pci.h" #include "pcie-designware.h" @@ -505,6 +506,9 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) if (pp->ops->post_init) pp->ops->post_init(pp); + pm_runtime_set_active(&bridge->dev); + pm_runtime_enable(&bridge->dev); + return 0; err_stop_link: --- base-commit: 6613476e225e090cc9aad49be7fa504e290dd33d change-id: 20240219-runtime_pm_enable-bdc17914bd50 Best regards, -- Krishna chaitanya chundru