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Tue, 12 Mar 2024 04:24:28 -0500 From: Wayne Lin To: CC: , , , , , , , , , , Nicholas Kazlauskas , Duncan Ma Subject: [PATCH 35/43] drm/amd/display: Detect and disallow idle reallow during reentrancy Date: Tue, 12 Mar 2024 17:20:28 +0800 Message-ID: <20240312092036.3283319-36-Wayne.Lin@amd.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20240312092036.3283319-1-Wayne.Lin@amd.com> References: <20240312092036.3283319-1-Wayne.Lin@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain Received-SPF: None (SATLEXMB03.amd.com: Wayne.Lin@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D6:EE_|SJ1PR12MB6049:EE_ X-MS-Office365-Filtering-Correlation-Id: 1f09d3b2-bce5-47de-d743-08dc42763abd X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: u8cFdJ+w8YhD5+MyIk3bDospiA9HAj1FTU/3lRMXm5mrL6EjaR61EVtBy56tzKfjO6n11gXaDkQF5NlZelHny/UqKhBxg4o7uSTdtQI7aiz4SmZS5Ibfcizs4Ghr3NkDDqylj969+iMU1u7b/1hCtA/Kj5n12QyfWL/gOcozoCtEFwgDBd+ZxwTBPi86MxP464atJiO0L2CW8fR3k/tdopGr6qq5zSA4/nCNF4r/hMllAY4nkXUP1CEt9vlOqrCm3BU62VPZHbXuHgHJ5ZJlAzVc7Y3TMpLqA1hwfcYfCsxQjh8+GNlVNfHCzDddWIFOLKFnN1rUpuCaUhTvodaIHC08XOsL1R45YB9D3ZzSFFw7gepCaZY9mp6Cwc/561fpvIzctLlXvGEUyl9CjM9k7GH+iunrrJv4S9Kc+/ZYZVsarEzWOyQ4QIhA9x0AgqGcQgrQ3cxAglMSRftDhhiZ48fdyox0eCOJ8e4zgoNj73jsC4QuszII0v6hPzvA1YP1MN6en68lcGOdvSGCFS6K2G6NVzwuyWRX2fbT0XmJFVsKJhPO2WoiP2FbzDc4d6wI3ADYSxJNfPJN0XobIALeFEt75NCa95Y1vyNcTsEFb6vq2WEiO1K5Kax6c5M99UiSrXNZRPZmFwKHdQJeaPb+GjI38xskpqyMBWd/l14UJwDnJVnwNFyDrfLgwrNk3njU5TEovYN8fF+sfVm8dsFf+WY2GKv9/qMqiZ+WtH3TDIH/EfvkalRf+CPib2KFIoyM X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB03.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230031)(36860700004)(1800799015)(376005)(82310400014); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Mar 2024 09:24:33.7768 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1f09d3b2-bce5-47de-d743-08dc42763abd X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D6.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR12MB6049 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" From: Nicholas Kazlauskas [Why] Cursor updates can be preempted by queued flips in some DMs. The synchronization model causes this to occur within the same thread at an intermediate level when we insert logs into the OS queue. Since this occurs on the same thread and we're still holding the lock (recursively) the cache is coherent. The exit sequence will run twice since we technically haven't finished the exit the first time, so we need a way to detect and avoid the reallow in the middle of this call to prevent the hang on the cursor update that was preempted. [How] Keep a counter that tracks the depth of the exit calls. Do not reallow until the counter is zero. Reviewed-by: Duncan Ma Acked-by: Wayne Lin Signed-off-by: Nicholas Kazlauskas --- drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 14 ++++++++++++-- drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h | 1 + 2 files changed, 13 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c index f796ed061879..4878e9e50440 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c +++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c @@ -1437,6 +1437,8 @@ void dc_dmub_srv_apply_idle_power_optimizations(const struct dc *dc, bool allow_ */ if (!allow_idle) { + dc_dmub_srv->idle_exit_counter += 1; + dc_dmub_srv_exit_low_power_state(dc); /* * Idle is considered fully exited only after the sequence above @@ -1448,6 +1450,12 @@ void dc_dmub_srv_apply_idle_power_optimizations(const struct dc *dc, bool allow_ * dm_execute_dmub_cmd submission instead of the "wake" helpers. */ dc_dmub_srv->idle_allowed = false; + + dc_dmub_srv->idle_exit_counter -= 1; + if (dc_dmub_srv->idle_exit_counter < 0) { + ASSERT(0); + dc_dmub_srv->idle_exit_counter = 0; + } } else { /* Consider idle as notified prior to the actual submission to * prevent multiple entries. */ @@ -1489,7 +1497,8 @@ bool dc_wake_and_execute_dmub_cmd_list(const struct dc_context *ctx, unsigned in else result = dm_execute_dmub_cmd(ctx, cmd, wait_type); - if (result && reallow_idle && !ctx->dc->debug.disable_dmub_reallow_idle) + if (result && reallow_idle && dc_dmub_srv->idle_exit_counter == 0 && + !ctx->dc->debug.disable_dmub_reallow_idle) dc_dmub_srv_apply_idle_power_optimizations(ctx->dc, true); return result; @@ -1538,7 +1547,8 @@ bool dc_wake_and_execute_gpint(const struct dc_context *ctx, enum dmub_gpint_com result = dc_dmub_execute_gpint(ctx, command_code, param, response, wait_type); - if (result && reallow_idle && !ctx->dc->debug.disable_dmub_reallow_idle) + if (result && reallow_idle && dc_dmub_srv->idle_exit_counter == 0 && + !ctx->dc->debug.disable_dmub_reallow_idle) dc_dmub_srv_apply_idle_power_optimizations(ctx->dc, true); return result; diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h index 60c93e9e3533..c0a512a12531 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h +++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h @@ -51,6 +51,7 @@ struct dc_dmub_srv { struct dc_context *ctx; void *dm; + int32_t idle_exit_counter; bool idle_allowed; bool needs_idle_wake; }; -- 2.37.3