From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from metis.whiteo.stw.pengutronix.de (metis.whiteo.stw.pengutronix.de [185.203.201.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B13F02C1B9 for ; Mon, 18 Mar 2024 10:00:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.203.201.7 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1710756016; cv=none; b=mSvQUXIQfwdG+w8oMOcxhzf0L7bwao5nuGt949E8GFFa2vAkZIiZbf312VAsGpze4uOgz9IKoyGjMiHfJ4NEsdmb9Axke0bDPIFg+lG31e1Y94LDmoaze3WXOoOPVn3X7DDttM/jEv0Wr0HXGwF+DhD+XP26ZSGzbWFuYlUjdOM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1710756016; c=relaxed/simple; bh=oHGAUUZInETu3uSOrSDkqyU5Ef2ZqZXmkK2RBU59St4=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=afBbJPc4rE7LLY0PlnQSHbz0P6MDl6kYaoZucklga9DboQNNGcluUo1zDOGmDGzdfqHfyjek19DktsUNkubU3NLWoLe4choSAHYlRF7IIyZRd7seKUQJFSAMhD43+WPCpGb1l/tByVoSyu4+omHWLv/llLkofLSJDx838oHgKkI= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de; spf=pass smtp.mailfrom=pengutronix.de; arc=none smtp.client-ip=185.203.201.7 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pengutronix.de Received: from drehscheibe.grey.stw.pengutronix.de ([2a0a:edc0:0:c01:1d::a2]) by metis.whiteo.stw.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1rm9mi-0003u1-8j; Mon, 18 Mar 2024 11:00:00 +0100 Received: from [2a0a:edc0:2:b01:1d::c5] (helo=pty.whiteo.stw.pengutronix.de) by drehscheibe.grey.stw.pengutronix.de with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1rm9mh-0073CL-KT; Mon, 18 Mar 2024 10:59:59 +0100 Received: from mfe by pty.whiteo.stw.pengutronix.de with local (Exim 4.96) (envelope-from ) id 1rm9mh-005SXP-1h; Mon, 18 Mar 2024 10:59:59 +0100 Date: Mon, 18 Mar 2024 10:59:59 +0100 From: Marco Felsch To: Peng Fan Cc: "Peng Fan (OSS)" , Abel Vesa , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , "imx@lists.linux.dev" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-clk@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" Subject: Re: [PATCH v4 0/6] Add support i.MX95 BLK CTL module clock features Message-ID: <20240318095959.v5d7qeoci5v2dtkq@pengutronix.de> References: <20240314-imx95-blk-ctl-v4-0-d23de23b6ff2@nxp.com> <20240317155911.pdc32nsyxcdhs2t7@pengutronix.de> Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: X-SA-Exim-Connect-IP: 2a0a:edc0:0:c01:1d::a2 X-SA-Exim-Mail-From: mfe@pengutronix.de X-SA-Exim-Scanned: No (on metis.whiteo.stw.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: imx@lists.linux.dev On 24-03-18, Peng Fan wrote: > Hi Marco, > > > Subject: Re: [PATCH v4 0/6] Add support i.MX95 BLK CTL module clock > > features > > > > Hi Peng, > > > > thank for the patchset. > > > > On 24-03-14, Peng Fan (OSS) wrote: > > > i.MX95's several MIXes has BLK CTL module which could be used for clk > > > settings, QoS settings, Misc settings for a MIX. This patchset is to > > > add the clk feature support, including dt-bindings > > > > I have to ask since there is almost no public documentation available yet. The > > i.MX95 does have an system-controller for managing pinmux settings and > > power-domains, right? > > Yes. > > If this is the case, why not making use of it via the > > standard scmi_pm_domain.c driver? > > The SCMI firmware not handle the BLK CTL stuff, but blk ctl stuff is > a mix of clk, qos, module specific things. It is not good for SCMI firmare > to handle it. Currently most of the blk-ctrl users do use the blk-ctrl as power-domain consumer, except for the isi and the audio part. So as I said above the scmi_pm_domain.c should be able to supply this. The audio blk-ctrl could be abstracted via the clk-scmi.c driver. The ISI is another topic. What you're are going to do here is to put pinctrl etc into SCMI firmware and power-control into Linux, which sound to me like an 50/50 approach and IMHO is rather sub-optimal. To quote your online available fact sheet: 8<---------------------------------------------------------- ENERGY FLEX ARCHITECTURE The i,MX 95 family is designed to be configurable and scalable, with multiple heterogenous processing domains. This includes an application domain with up to 6 Arm Cortex A55 cores, a high-performance real-time domain with Arm Cortex M7, and low-power/safety domain with Arm Cortex M33, each able to access interfaces including CAN-FD, 10GbE networking, PCIe Gen 3 x1 interfaces, and accelerators such as V2X, ISP, and VPU. 8<---------------------------------------------------------- 8<---------------------------------------------------------- HIGH-PERFORMANCE COMPUTE The i.MX 95 family capabilities include a multi-core application domain with up to six Arm Cortex®-A55 cores, as well as two independent real-time domains for safety/low-power, and high-performance real-time use, consisting of high-performance Arm Cortex-M7 and Arm Cortex-M33 CPUs, combining low-power, real-time, and high-performance processing. The i.MX 95 family is designed to enable ISO 26262 ASIL-B and SIL-2 IEC 61508 compliant platforms, with the safety domain serving as a critical capability for many automotive and industrial applications. ... 8<---------------------------------------------------------- To me this sound like we can turn of the power/clock of an hardware block which was assigned to a core running SIL-2 certified software from an non-critical core running Linux if we follow that approach. Also the SIL-2 software requires the non-critical software to turn on the power of these hardware blocks. Is this correct? Regards, Marco > Regards, > Peng. > > > > > Regards, > > Marco > > > > > > > > > > > > Signed-off-by: Peng Fan > > > --- > > > Changes in v4: > > > - Separate binding doc for each modules, I still keep the syscon as > > > node name, because the module is not just for clock > > > - Pass dt-schema check > > > - Update node compatibles > > > - Link to v3: > > > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore > > > .kernel.org%2Fr%2F20240228-imx95-blk-ctl-v3-0- > > 40ceba01a211%40nxp.com&d > > > > > ata=05%7C02%7Cpeng.fan%40nxp.com%7Caad977d7e4f94c750de408dc469 > > b3952%7C > > > > > 686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C63846287969085566 > > 1%7CUnknow > > > > > n%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1ha > > WwiLC > > > > > JXVCI6Mn0%3D%7C0%7C%7C%7C&sdata=M%2B3lDY9BKvW0nHv4mtvi82RA > > 9IvYyz72TCbL > > > UpiYcG0%3D&reserved=0 > > > > > > Changes in v3: > > > - Correct example node compatible string > > > - Pass "make ARCH=arm64 DT_CHECKER_FLAGS=-m -j32 dt_binding_check" > > > - Link to v2: > > > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore > > > .kernel.org%2Fr%2F20240228-imx95-blk-ctl-v2-0- > > ffb7eefb6dcd%40nxp.com&d > > > > > ata=05%7C02%7Cpeng.fan%40nxp.com%7Caad977d7e4f94c750de408dc469 > > b3952%7C > > > > > 686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C63846287969086560 > > 2%7CUnknow > > > > > n%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1ha > > WwiLC > > > > > JXVCI6Mn0%3D%7C0%7C%7C%7C&sdata=4leg49tKhwUMzvD5wlnvgVc7is%2 > > FGMNvpYr6A > > > %2FAf3OU4%3D&reserved=0 > > > > > > Changes in v2: > > > - Correct example node compatible string > > > - Link to v1: > > > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore > > > .kernel.org%2Fr%2F20240228-imx95-blk-ctl-v1-0- > > 9b5ae3c14d83%40nxp.com&d > > > > > ata=05%7C02%7Cpeng.fan%40nxp.com%7Caad977d7e4f94c750de408dc469 > > b3952%7C > > > > > 686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C63846287969087217 > > 2%7CUnknow > > > > > n%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1ha > > WwiLC > > > > > JXVCI6Mn0%3D%7C0%7C%7C%7C&sdata=UuD5MVPFgBqwftuXCIXB7SeGyu0 > > NWPbwY%2Bvy > > > ChFLyVA%3D&reserved=0 > > > > > > --- > > > Peng Fan (6): > > > dt-bindindgs: clock: nxp: support i.MX95 VPU CSR module > > > dt-bindindgs: clock: nxp: support i.MX95 Camera CSR module > > > dt-bindindgs: clock: nxp: support i.MX95 Display Master CSR module > > > dt-bindindgs: clock: nxp: support i.MX95 LVDS CSR module > > > dt-bindindgs: clock: nxp: support i.MX95 Display CSR module > > > clk: imx: add i.MX95 BLK CTL clk driver > > > > > > .../bindings/clock/nxp,imx95-camera-csr.yaml | 50 +++ > > > .../bindings/clock/nxp,imx95-display-csr.yaml | 50 +++ > > > .../clock/nxp,imx95-display-master-csr.yaml | 62 +++ > > > .../bindings/clock/nxp,imx95-lvds-csr.yaml | 50 +++ > > > .../bindings/clock/nxp,imx95-vpu-csr.yaml | 50 +++ > > > drivers/clk/imx/Kconfig | 7 + > > > drivers/clk/imx/Makefile | 1 + > > > drivers/clk/imx/clk-imx95-blk-ctl.c | 438 +++++++++++++++++++++ > > > include/dt-bindings/clock/nxp,imx95-clock.h | 32 ++ > > > 9 files changed, 740 insertions(+) > > > --- > > > base-commit: c9c32620af65fee2b1ac8390fe1349b33f9d0888 > > > change-id: 20240228-imx95-blk-ctl-9ef8c1fc4c22 > > > > > > Best regards, > > > -- > > > Peng Fan > > > > > > > > > > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 600BEC54E58 for ; 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Mon, 18 Mar 2024 10:00:26 +0000 Received: from metis.whiteo.stw.pengutronix.de ([2a0a:edc0:2:b01:1d::104]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rm9n4-000000082g2-2qRj for linux-arm-kernel@lists.infradead.org; Mon, 18 Mar 2024 10:00:24 +0000 Received: from drehscheibe.grey.stw.pengutronix.de ([2a0a:edc0:0:c01:1d::a2]) by metis.whiteo.stw.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1rm9mi-0003u1-8j; Mon, 18 Mar 2024 11:00:00 +0100 Received: from [2a0a:edc0:2:b01:1d::c5] (helo=pty.whiteo.stw.pengutronix.de) by drehscheibe.grey.stw.pengutronix.de with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1rm9mh-0073CL-KT; Mon, 18 Mar 2024 10:59:59 +0100 Received: from mfe by pty.whiteo.stw.pengutronix.de with local (Exim 4.96) (envelope-from ) id 1rm9mh-005SXP-1h; Mon, 18 Mar 2024 10:59:59 +0100 Date: Mon, 18 Mar 2024 10:59:59 +0100 From: Marco Felsch To: Peng Fan Cc: "Peng Fan (OSS)" , Abel Vesa , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , "imx@lists.linux.dev" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-clk@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" Subject: Re: [PATCH v4 0/6] Add support i.MX95 BLK CTL module clock features Message-ID: <20240318095959.v5d7qeoci5v2dtkq@pengutronix.de> References: <20240314-imx95-blk-ctl-v4-0-d23de23b6ff2@nxp.com> <20240317155911.pdc32nsyxcdhs2t7@pengutronix.de> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-SA-Exim-Connect-IP: 2a0a:edc0:0:c01:1d::a2 X-SA-Exim-Mail-From: mfe@pengutronix.de X-SA-Exim-Scanned: No (on metis.whiteo.stw.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-arm-kernel@lists.infradead.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240318_030022_975954_8AFD9302 X-CRM114-Status: GOOD ( 30.05 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 24-03-18, Peng Fan wrote: > Hi Marco, > = > > Subject: Re: [PATCH v4 0/6] Add support i.MX95 BLK CTL module clock > > features > > = > > Hi Peng, > > = > > thank for the patchset. > > = > > On 24-03-14, Peng Fan (OSS) wrote: > > > i.MX95's several MIXes has BLK CTL module which could be used for clk > > > settings, QoS settings, Misc settings for a MIX. This patchset is to > > > add the clk feature support, including dt-bindings > > = > > I have to ask since there is almost no public documentation available y= et. The > > i.MX95 does have an system-controller for managing pinmux settings and > > power-domains, right? = > = > Yes. = > = > If this is the case, why not making use of it via the > > standard scmi_pm_domain.c driver? > = > The SCMI firmware not handle the BLK CTL stuff, but blk ctl stuff is > a mix of clk, qos, module specific things. It is not good for SCMI firmare > to handle it. Currently most of the blk-ctrl users do use the blk-ctrl as power-domain consumer, except for the isi and the audio part. So as I said above the scmi_pm_domain.c should be able to supply this. The audio blk-ctrl could be abstracted via the clk-scmi.c driver. The ISI is another topic. What you're are going to do here is to put pinctrl etc into SCMI firmware and power-control into Linux, which sound to me like an 50/50 approach and IMHO is rather sub-optimal. To quote your online available fact sheet: 8<---------------------------------------------------------- ENERGY FLEX ARCHITECTURE The i,MX 95 family is designed to be configurable and scalable, with multiple heterogenous processing domains. This includes an application domain with up to 6 Arm Cortex A55 cores, a high-performance real-time domain with Arm Cortex M7, and low-power/safety domain with Arm Cortex M33, each able to access interfaces including CAN-FD, 10GbE networking, PCIe Gen 3 x1 interfaces, and accelerators such as V2X, ISP, and VPU. 8<---------------------------------------------------------- 8<---------------------------------------------------------- HIGH-PERFORMANCE COMPUTE The i.MX 95 family capabilities include a multi-core application domain with up to six Arm Cortex=AE-A55 cores, as well as two independent real-time domains for safety/low-power, and high-performance real-time use, consisting of high-performance Arm Cortex-M7 and Arm Cortex-M33 CPUs, combining low-power, real-time, and high-performance processing. The i.MX 95 family is designed to enable ISO 26262 ASIL-B and SIL-2 IEC 61508 compliant platforms, with the safety domain serving as a critical capability for many automotive and industrial applications. ... 8<---------------------------------------------------------- To me this sound like we can turn of the power/clock of an hardware block which was assigned to a core running SIL-2 certified software from an non-critical core running Linux if we follow that approach. Also the SIL-2 software requires the non-critical software to turn on the power of these hardware blocks. Is this correct? Regards, Marco > Regards, > Peng. > = > > = > > Regards, > > Marco > > = > > = > > = > > > > > > Signed-off-by: Peng Fan > > > --- > > > Changes in v4: > > > - Separate binding doc for each modules, I still keep the syscon as > > > node name, because the module is not just for clock > > > - Pass dt-schema check > > > - Update node compatibles > > > - Link to v3: > > > https://eur01.safelinks.protection.outlook.com/?url=3Dhttps%3A%2F%2Fl= ore > > > .kernel.org%2Fr%2F20240228-imx95-blk-ctl-v3-0- > > 40ceba01a211%40nxp.com&d > > > > > ata=3D05%7C02%7Cpeng.fan%40nxp.com%7Caad977d7e4f94c750de408dc469 > > b3952%7C > > > > > 686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C63846287969085566 > > 1%7CUnknow > > > > > n%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1ha > > WwiLC > > > > > JXVCI6Mn0%3D%7C0%7C%7C%7C&sdata=3DM%2B3lDY9BKvW0nHv4mtvi82RA > > 9IvYyz72TCbL > > > UpiYcG0%3D&reserved=3D0 > > > > > > Changes in v3: > > > - Correct example node compatible string > > > - Pass "make ARCH=3Darm64 DT_CHECKER_FLAGS=3D-m -j32 dt_binding_check" > > > - Link to v2: > > > https://eur01.safelinks.protection.outlook.com/?url=3Dhttps%3A%2F%2Fl= ore > > > .kernel.org%2Fr%2F20240228-imx95-blk-ctl-v2-0- > > ffb7eefb6dcd%40nxp.com&d > > > > > ata=3D05%7C02%7Cpeng.fan%40nxp.com%7Caad977d7e4f94c750de408dc469 > > b3952%7C > > > > > 686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C63846287969086560 > > 2%7CUnknow > > > > > n%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1ha > > WwiLC > > > > > JXVCI6Mn0%3D%7C0%7C%7C%7C&sdata=3D4leg49tKhwUMzvD5wlnvgVc7is%2 > > FGMNvpYr6A > > > %2FAf3OU4%3D&reserved=3D0 > > > > > > Changes in v2: > > > - Correct example node compatible string > > > - Link to v1: > > > https://eur01.safelinks.protection.outlook.com/?url=3Dhttps%3A%2F%2Fl= ore > > > .kernel.org%2Fr%2F20240228-imx95-blk-ctl-v1-0- > > 9b5ae3c14d83%40nxp.com&d > > > > > ata=3D05%7C02%7Cpeng.fan%40nxp.com%7Caad977d7e4f94c750de408dc469 > > b3952%7C > > > > > 686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C63846287969087217 > > 2%7CUnknow > > > > > n%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1ha > > WwiLC > > > > > JXVCI6Mn0%3D%7C0%7C%7C%7C&sdata=3DUuD5MVPFgBqwftuXCIXB7SeGyu0 > > NWPbwY%2Bvy > > > ChFLyVA%3D&reserved=3D0 > > > > > > --- > > > Peng Fan (6): > > > dt-bindindgs: clock: nxp: support i.MX95 VPU CSR module > > > dt-bindindgs: clock: nxp: support i.MX95 Camera CSR module > > > dt-bindindgs: clock: nxp: support i.MX95 Display Master CSR mod= ule > > > dt-bindindgs: clock: nxp: support i.MX95 LVDS CSR module > > > dt-bindindgs: clock: nxp: support i.MX95 Display CSR module > > > clk: imx: add i.MX95 BLK CTL clk driver > > > > > > .../bindings/clock/nxp,imx95-camera-csr.yaml | 50 +++ > > > .../bindings/clock/nxp,imx95-display-csr.yaml | 50 +++ > > > .../clock/nxp,imx95-display-master-csr.yaml | 62 +++ > > > .../bindings/clock/nxp,imx95-lvds-csr.yaml | 50 +++ > > > .../bindings/clock/nxp,imx95-vpu-csr.yaml | 50 +++ > > > drivers/clk/imx/Kconfig | 7 + > > > drivers/clk/imx/Makefile | 1 + > > > drivers/clk/imx/clk-imx95-blk-ctl.c | 438 +++++++++++= ++++++++++ > > > include/dt-bindings/clock/nxp,imx95-clock.h | 32 ++ > > > 9 files changed, 740 insertions(+) > > > --- > > > base-commit: c9c32620af65fee2b1ac8390fe1349b33f9d0888 > > > change-id: 20240228-imx95-blk-ctl-9ef8c1fc4c22 > > > > > > Best regards, > > > -- > > > Peng Fan > > > > > > > > > > = _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel