From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from metis.whiteo.stw.pengutronix.de (metis.whiteo.stw.pengutronix.de [185.203.201.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0645C50A80 for ; Tue, 19 Mar 2024 07:17:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.203.201.7 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1710832663; cv=none; b=dovjqAExmQG9wcdHEwuUxgp3hf+3eXLGSxG+U77FBMKabmztK0+1J9dusI7frTEmwoq28hnBjwK4OjvhtRvQMJ7B6gEunoVNw0hSQTSAEEcsd2zUSkL2YbbR6tRGuhYhgpXakXxfYyxCho3qX4yL0mbQgjOx00vMsJmf8+S4mVg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1710832663; c=relaxed/simple; bh=RFYP/L80IkesCq4S5f/hEdGLshAkHKf2HOddb5Qa1hA=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=N+yL693HxF4Si9hNxqRCShDnzELdckK6X4uvG6xDqcaqyLZOcRKNyKPN+N27AmzwJTQTtXqhgfMFRfihResg5ewBbS/Zz0nibFsleSEROT4Q7MgvTJZtF0LnAc0J3VYPPseiHWdKriq68aEJ5VLgBXhuWERUlVFUrNH5tZ+mxzE= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de; spf=pass smtp.mailfrom=pengutronix.de; arc=none smtp.client-ip=185.203.201.7 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pengutronix.de Received: from drehscheibe.grey.stw.pengutronix.de ([2a0a:edc0:0:c01:1d::a2]) by metis.whiteo.stw.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1rmTix-0007aO-GN; Tue, 19 Mar 2024 08:17:27 +0100 Received: from [2a0a:edc0:2:b01:1d::c5] (helo=pty.whiteo.stw.pengutronix.de) by drehscheibe.grey.stw.pengutronix.de with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1rmTiu-007EBK-Vy; Tue, 19 Mar 2024 08:17:25 +0100 Received: from mfe by pty.whiteo.stw.pengutronix.de with local (Exim 4.96) (envelope-from ) id 1rmTiu-006xkf-2m; Tue, 19 Mar 2024 08:17:24 +0100 Date: Tue, 19 Mar 2024 08:17:24 +0100 From: Marco Felsch To: Peng Fan Cc: "Peng Fan (OSS)" , Abel Vesa , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , "imx@lists.linux.dev" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-clk@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" Subject: Re: [PATCH v4 0/6] Add support i.MX95 BLK CTL module clock features Message-ID: <20240319071724.6n4vpbkmddejksd5@pengutronix.de> References: <20240314-imx95-blk-ctl-v4-0-d23de23b6ff2@nxp.com> <20240317155911.pdc32nsyxcdhs2t7@pengutronix.de> <20240318095959.v5d7qeoci5v2dtkq@pengutronix.de> <20240318140742.3pfn5h6wqhbtgbmj@pengutronix.de> Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-SA-Exim-Connect-IP: 2a0a:edc0:0:c01:1d::a2 X-SA-Exim-Mail-From: mfe@pengutronix.de X-SA-Exim-Scanned: No (on metis.whiteo.stw.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: imx@lists.linux.dev On 24-03-18, Peng Fan wrote: > > > > To me this sound like we can turn of the power/clock of an hardware > > > > block which was assigned to a core running SIL-2 certified software > > > > from an non- critical core running Linux if we follow that approach. > > > > Also the > > > > SIL-2 software requires the non-critical software to turn on the > > > > power of these hardware blocks. Is this correct? > > > > > > Non-critical software not able to turn off power/clock of a critical > > > resource in safety software domain. > > > Safety software not require non-safety software to turn on power/clocks. > > > > Due to lack of documentation I don't know how you implemented this in > > HW/SW, also the system-design is telling us which parts should be seen as > > safe and which don't. However I get your point, VPUMIX is not going to be a > > part of the safe partition albeit it "could" due to complexity. > > If safe function needs VPU feature, VPUMIX could be totally assigned to M7 > core through TRDC isolation, not assigned its BLK CTRL to system controller > core. Thanks for the clarification :) Regards, Marco From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3F00DC54E60 for ; Tue, 19 Mar 2024 07:18:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=yUWl+UrZDQl/PcbghCGFWFuUjM3PSewwBEOPByDKA08=; b=zjNy2VPnC0ZTty q11DctM98GBmhSYKZFt/us4B+Ry0uPrUcOL13kvqPJvq4XA7iQR63+mEEcaHK4CaZoe4d3LF1NZi7 5qsye3ixnKlTm8stFYSB3RoPdFNIfZF/mwR0iMtfd1p5csDiBDYIZIVCt3o6oS1d0qvdiou4i65Sd Rq5OrrS5C6X9JunLj3MF3p6Y/fnq1hPX/oFw5CAMM+pvbpJ/WyoXu2YJzzLJZM48ZhsQOvF9OEvL8 /68eNREi2a5ixBlggPeS6OAeyWcTYHCf+g15H3+jVCh0C2PILvmYmSUqwjCfPfIz/C83r2Xs0HnI3 3oU4N59XS08SxMRfIzeA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rmTjO-0000000BfuT-0Wtc; Tue, 19 Mar 2024 07:17:54 +0000 Received: from metis.whiteo.stw.pengutronix.de ([2a0a:edc0:2:b01:1d::104]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rmTjK-0000000Bfsg-23T9 for linux-arm-kernel@lists.infradead.org; Tue, 19 Mar 2024 07:17:52 +0000 Received: from drehscheibe.grey.stw.pengutronix.de ([2a0a:edc0:0:c01:1d::a2]) by metis.whiteo.stw.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1rmTix-0007aO-GN; Tue, 19 Mar 2024 08:17:27 +0100 Received: from [2a0a:edc0:2:b01:1d::c5] (helo=pty.whiteo.stw.pengutronix.de) by drehscheibe.grey.stw.pengutronix.de with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1rmTiu-007EBK-Vy; Tue, 19 Mar 2024 08:17:25 +0100 Received: from mfe by pty.whiteo.stw.pengutronix.de with local (Exim 4.96) (envelope-from ) id 1rmTiu-006xkf-2m; Tue, 19 Mar 2024 08:17:24 +0100 Date: Tue, 19 Mar 2024 08:17:24 +0100 From: Marco Felsch To: Peng Fan Cc: "Peng Fan (OSS)" , Abel Vesa , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , "imx@lists.linux.dev" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-clk@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" Subject: Re: [PATCH v4 0/6] Add support i.MX95 BLK CTL module clock features Message-ID: <20240319071724.6n4vpbkmddejksd5@pengutronix.de> References: <20240314-imx95-blk-ctl-v4-0-d23de23b6ff2@nxp.com> <20240317155911.pdc32nsyxcdhs2t7@pengutronix.de> <20240318095959.v5d7qeoci5v2dtkq@pengutronix.de> <20240318140742.3pfn5h6wqhbtgbmj@pengutronix.de> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-SA-Exim-Connect-IP: 2a0a:edc0:0:c01:1d::a2 X-SA-Exim-Mail-From: mfe@pengutronix.de X-SA-Exim-Scanned: No (on metis.whiteo.stw.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-arm-kernel@lists.infradead.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240319_001750_548386_9B92BA68 X-CRM114-Status: GOOD ( 18.11 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 24-03-18, Peng Fan wrote: > > > > To me this sound like we can turn of the power/clock of an hardware > > > > block which was assigned to a core running SIL-2 certified software > > > > from an non- critical core running Linux if we follow that approach. > > > > Also the > > > > SIL-2 software requires the non-critical software to turn on the > > > > power of these hardware blocks. Is this correct? > > > > > > Non-critical software not able to turn off power/clock of a critical > > > resource in safety software domain. > > > Safety software not require non-safety software to turn on power/clocks. > > > > Due to lack of documentation I don't know how you implemented this in > > HW/SW, also the system-design is telling us which parts should be seen as > > safe and which don't. However I get your point, VPUMIX is not going to be a > > part of the safe partition albeit it "could" due to complexity. > > If safe function needs VPU feature, VPUMIX could be totally assigned to M7 > core through TRDC isolation, not assigned its BLK CTRL to system controller > core. Thanks for the clarification :) Regards, Marco _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel