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Tue, 19 Mar 2024 14:59:16 -0700 (PDT) Received: from sw06.internal.sifive.com ([4.53.31.132]) by smtp.gmail.com with ESMTPSA id z25-20020aa785d9000000b006e6c61b264bsm10273892pfn.32.2024.03.19.14.59.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Mar 2024 14:59:16 -0700 (PDT) From: Samuel Holland To: Palmer Dabbelt , linux-riscv@lists.infradead.org Cc: devicetree@vger.kernel.org, Catalin Marinas , linux-kernel@vger.kernel.org, tech-j-ext@lists.risc-v.org, Conor Dooley , kasan-dev@googlegroups.com, Evgenii Stepanov , Krzysztof Kozlowski , Rob Herring , Samuel Holland , Albert Ou , Andrew Jones Subject: [RFC PATCH 0/9] riscv: Userspace pointer masking and tagged address ABI Date: Tue, 19 Mar 2024 14:58:26 -0700 Message-ID: <20240319215915.832127-1-samuel.holland@sifive.com> X-Mailer: git-send-email 2.43.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit RISC-V defines three extensions for pointer masking[1]: - Smmpm: configured in M-mode, affects M-mode - Smnpm: configured in M-mode, affects the next lower mode (S or U-mode) - Ssnpm: configured in S-mode, affects the next lower mode (U-mode) This series adds support for configuring Smnpm or Ssnpm (depending on which mode the kernel is running in) to allow pointer masking in userspace by extending the existing PR_SET_TAGGED_ADDR_CTRL API from arm64. Unlike arm64 TBI, userspace pointer masking is not enabled by default on RISC-V. Additionally, the tag width (referred to as PMLEN) is variable, so userspace needs to ask the kernel for a specific tag width (which is interpreted as a minimum number of tag bits). This series also adds support for a tagged address ABI similar to arm64. Since accesses from the kernel to user memory use the kernel's pointer masking configuration, not the user's, the kernel must untag user pointers in software before dereferencing them. This series can be tested in QEMU by applying a patch set[2]. KASAN support is not included here because there is not yet any standard way for the kernel to ask firmware to enable pointer masking in S-mode. [1]: https://github.com/riscv/riscv-j-extension/raw/a1e68469c60/zjpm-spec.pdf [2]: https://patchwork.kernel.org/project/qemu-devel/list/?series=822467&archive=both Samuel Holland (9): dt-bindings: riscv: Add pointer masking ISA extensions riscv: Add ISA extension parsing for pointer masking riscv: Add CSR definitions for pointer masking riscv: Define is_compat_thread() riscv: Split per-CPU and per-thread envcfg bits riscv: Add support for userspace pointer masking riscv: Add support for the tagged address ABI riscv: Allow ptrace control of the tagged address ABI selftests: riscv: Add a pointer masking test .../devicetree/bindings/riscv/extensions.yaml | 18 + arch/riscv/Kconfig | 8 + arch/riscv/include/asm/compat.h | 16 + arch/riscv/include/asm/cpufeature.h | 2 + arch/riscv/include/asm/csr.h | 16 + arch/riscv/include/asm/hwcap.h | 5 + arch/riscv/include/asm/processor.h | 10 + arch/riscv/include/asm/switch_to.h | 12 + arch/riscv/include/asm/uaccess.h | 40 ++- arch/riscv/kernel/cpufeature.c | 7 +- arch/riscv/kernel/process.c | 154 +++++++++ arch/riscv/kernel/ptrace.c | 42 +++ include/uapi/linux/elf.h | 1 + include/uapi/linux/prctl.h | 3 + tools/testing/selftests/riscv/Makefile | 2 +- tools/testing/selftests/riscv/tags/Makefile | 10 + .../selftests/riscv/tags/pointer_masking.c | 307 ++++++++++++++++++ 17 files changed, 646 insertions(+), 7 deletions(-) create mode 100644 tools/testing/selftests/riscv/tags/Makefile create mode 100644 tools/testing/selftests/riscv/tags/pointer_masking.c -- 2.43.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 58EC4C54E68 for ; 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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org RISC-V defines three extensions for pointer masking[1]: - Smmpm: configured in M-mode, affects M-mode - Smnpm: configured in M-mode, affects the next lower mode (S or U-mode) - Ssnpm: configured in S-mode, affects the next lower mode (U-mode) This series adds support for configuring Smnpm or Ssnpm (depending on which mode the kernel is running in) to allow pointer masking in userspace by extending the existing PR_SET_TAGGED_ADDR_CTRL API from arm64. Unlike arm64 TBI, userspace pointer masking is not enabled by default on RISC-V. Additionally, the tag width (referred to as PMLEN) is variable, so userspace needs to ask the kernel for a specific tag width (which is interpreted as a minimum number of tag bits). This series also adds support for a tagged address ABI similar to arm64. Since accesses from the kernel to user memory use the kernel's pointer masking configuration, not the user's, the kernel must untag user pointers in software before dereferencing them. This series can be tested in QEMU by applying a patch set[2]. KASAN support is not included here because there is not yet any standard way for the kernel to ask firmware to enable pointer masking in S-mode. [1]: https://github.com/riscv/riscv-j-extension/raw/a1e68469c60/zjpm-spec.pdf [2]: https://patchwork.kernel.org/project/qemu-devel/list/?series=822467&archive=both Samuel Holland (9): dt-bindings: riscv: Add pointer masking ISA extensions riscv: Add ISA extension parsing for pointer masking riscv: Add CSR definitions for pointer masking riscv: Define is_compat_thread() riscv: Split per-CPU and per-thread envcfg bits riscv: Add support for userspace pointer masking riscv: Add support for the tagged address ABI riscv: Allow ptrace control of the tagged address ABI selftests: riscv: Add a pointer masking test .../devicetree/bindings/riscv/extensions.yaml | 18 + arch/riscv/Kconfig | 8 + arch/riscv/include/asm/compat.h | 16 + arch/riscv/include/asm/cpufeature.h | 2 + arch/riscv/include/asm/csr.h | 16 + arch/riscv/include/asm/hwcap.h | 5 + arch/riscv/include/asm/processor.h | 10 + arch/riscv/include/asm/switch_to.h | 12 + arch/riscv/include/asm/uaccess.h | 40 ++- arch/riscv/kernel/cpufeature.c | 7 +- arch/riscv/kernel/process.c | 154 +++++++++ arch/riscv/kernel/ptrace.c | 42 +++ include/uapi/linux/elf.h | 1 + include/uapi/linux/prctl.h | 3 + tools/testing/selftests/riscv/Makefile | 2 +- tools/testing/selftests/riscv/tags/Makefile | 10 + .../selftests/riscv/tags/pointer_masking.c | 307 ++++++++++++++++++ 17 files changed, 646 insertions(+), 7 deletions(-) create mode 100644 tools/testing/selftests/riscv/tags/Makefile create mode 100644 tools/testing/selftests/riscv/tags/pointer_masking.c -- 2.43.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv