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(unknown [78.208.223.3]) by zproxy3.enst.fr (Postfix) with ESMTPSA id 5245AA014E; Sun, 24 Mar 2024 17:56:16 +0100 (CET) From: Arnaud Minier To: qemu-devel@nongnu.org Cc: Laurent Vivier , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , qemu-arm@nongnu.org, Paolo Bonzini , Alistair Francis , Arnaud Minier , Thomas Huth , =?UTF-8?q?In=C3=A8s=20Varhol?= , Samuel Tardieu , Peter Maydell Subject: [PATCH v2 0/6] hw/char: Implement the STM32L4x5 USART, UART and LPUART Date: Sun, 24 Mar 2024 17:55:40 +0100 Message-Id: <20240324165545.201908-1-arnaud.minier@telecom-paris.fr> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2001:660:330f:2::de; envelope-from=arnaud.minier@telecom-paris.fr; helo=zproxy3.enst.fr X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This patch adds the STM32L4x5 USART (Universal Synchronous/Asynchronous Receiver/Transmitter) device and is part of a series implementing the STM32L4x5 with a few peripherals. It implements the necessary functionalities to receive/send characters over the serial port, which are useful to communicate with the program currently running. Many thanks Peter for your review, I think I addressed almost everything. I'm just unsure about how to handle the waiting time in the tests. I understand your concerns about the unreliability of using the wallclock time but I don't understand how using clock_step() would make it more reliable. We will always be waiting on something that is out of our control (i.e. the OS). I increased the delay from 5s to 10min to match the microbit test and added a comment (I paraphrased your comment, is that okay ?). I also saw that Philippe Mathieu-Daud=C3=A9 have sent a patchset with the first commit of this patchset and another commit to make clock_set_mul_div() return a boolean. If this is merged before this patchset (which will probably be the case), I will remove the first commit. Changes from v1 to v2: - Use asynchronous transmission for serial communication (based on cmsdk-apb-uart implementation) - Use qemu_log_mask instead of error_report - Squash the commit that renamed the base struct - Use switch statements where appropriate - Fix RDR and TDR mask size - Increase time limit in tests - Remove the global qtest in the tests - Use assert when checking the interrupt number in the tests - Correct usage of g_autofree in the SoC Arnaud Minier (6): hw/misc/stm32l4x5_rcc: Propagate period when enabling a clock hw/char: Implement STM32L4x5 USART skeleton hw/char/stm32l4x5_usart: Enable serial read and write hw/char/stm32l4x5_usart: Add options for serial parameters setting hw/arm: Add the USART to the stm32l4x5 SoC tests/qtest: Add tests for the STM32L4x5 USART MAINTAINERS | 1 + docs/system/arm/b-l475e-iot01a.rst | 2 +- hw/arm/Kconfig | 1 + hw/arm/stm32l4x5_soc.c | 82 +++- hw/char/Kconfig | 3 + hw/char/meson.build | 1 + hw/char/stm32l4x5_usart.c | 632 +++++++++++++++++++++++++++++ hw/char/trace-events | 12 + hw/misc/stm32l4x5_rcc.c | 7 +- include/hw/arm/stm32l4x5_soc.h | 13 + include/hw/char/stm32l4x5_usart.h | 67 +++ tests/qtest/meson.build | 3 +- tests/qtest/stm32l4x5_usart-test.c | 326 +++++++++++++++ 13 files changed, 1141 insertions(+), 9 deletions(-) create mode 100644 hw/char/stm32l4x5_usart.c create mode 100644 include/hw/char/stm32l4x5_usart.h create mode 100644 tests/qtest/stm32l4x5_usart-test.c --=20 2.34.1